Quote Originally Posted by Splave View Post
so there is a point where lowering subtimings that you will actually be slower? because it will just disregard the value that you entered if it is too low?
Depends what Intel do at the IMC end, the chipset will have to issue the correct spacing. Whether or not that adds a larger delay you guys will have to test. Most of the timings are 4 clock limited due to the length of a burst and will revert to that even though the register set allows lower numbers to be inputted (internally these will = 4). Depending on the vendor, the timing ranges can be different (1 may = 4 and 2 = 5 instead of 4=4 and 1,2,3 just reverting to 4). When the DQ lines are toggling, you cannot send certain commands to the same bank.