SuperPi32m 5Ghz Ivy All Out Challenge!

[Raja@ASUS]

IMO that's too cut n dried. I've found plenty of examples over the years where IC density has dictated that tRAS has to be increased for stability before any other primary timing.... but too much takes the stability away again.

(assuming the user doesn't want to increase any voltages further)

tRAS merely alerts for the next row activate to the same bank - a page close. And "too much" should have no negative impact on stability unless one has mismatched tRC. What I provided above is the optimum for a page close scenario.

The rest of the performance impact and gains come down to the scheduling and reordering capabilities of the chipset and the corresponding IO capabilities of the DIMMs. On these architectures (and I do believe we are talking about IB in this thread at least), CAS takes general precedence over tRAS as there will be far fewer page misses than column reads The re-orderng here is a lot more efficient than what we have known in the past.


When a user is tapped out for CAS, then the only option is to start looking into the lesser timings.