SuperPi32m 5Ghz Ivy All Out Challenge!

[trans am]

@honda I got the ssd back from samsung. I need to talk to you about ocx tuner. I never ever made partitions on an ssd before as far as I know its a nono but regardless, I made 2 partitions on the 830. one for stripped xp and one for waza.
what settings do you recommend for osx on a ssd? My raptor is fubar and all i have left are ssd these are my settings..
I think I'm missing something.

@ CN guys give this dude some praise. he came in out of nowhere on a 3570 and got 6.25.
I think that deserves a shout.

i didnt install the chipset drivers. does it matter?

[mike]

is server 2003 faster than xp? i see alot of talks and screen shots. mabye im on wrong os

running 2003 here ... trying to figure out if XP might be better myself....



mike - 6:23:469 - 50x100 - 1067MHz - 7-7-6-20 - Gigabyte Z77X-UD3H - Corsair Dead Hypers Dominators 2000C7 - 1.72v - 180W pelt cooled ram

[rouvio]

I'll be away from my rig for about a week can't participate, yet.
will do my best to give a challenge

[MaJ0r]

A little improvement
MaJ0r 6:20:609 46x108.7 1304 9-12-8-29 Kingston DDR3 2333 Elpida BCBG DJ-F(I think) 1.8V air ASUS Maximus 5 Gene

[MaJ0r]

I cannot break the magic 6:20 lol tried all weekend. 6:20.076 ftl

Splave come on you can do this
Btw, I know one tweak if i had memory like you I'll broke 6.20 barrier

[dinos22]

is server 2003 faster than xp? i see alot of talks and screen shots. mabye im on wrong os

tested tonight, no difference man

[dinos22]

Splave come on you can do this
Btw, I know one tweak if i had memory like you I'll broke 6.20 barrier

your setup should do sub 20s

[MaJ0r]

your setup should do sub 20s

Maybe, but I can't do better. I have to learn tweaking better or I don't know something. Maybe GBT board is faster? ))

[Raja@ASUS]

Maybe, but I can't do better. I have to learn tweaking better or I don't know something. Maybe GBT board is faster? ))

tRAS= should be tRCD+CAS+tRTP. If DIMMs can do it then tRCD+CAS+2 (anything lower the chipset will issue a minimum delay on that will default to tBurst active time).

tFAW=16 if tRRD is 4.

This will speed up the run a bit.


tRCD 12 is a bit loose with CAS 9 at that freq.

The rest comes down to how optimised the OS is and Waza.

[MaJ0r]

tRAS= should be tRCD+CAS+tRTP. If DIMMs can do it then tRCD+CAS+2

tFAW=16 if tRRD is 4.

This will speed up the run a bit.


tRCD 12 is a bit loose with CAS 9 at that freq.

The rest comes down to how optimised the OS is and Waza.

Thanks but TRas=29 is a minimun for this frequency, no chances to set lower. Maybe I could set Tfaw=16 I didn't try. tRCD=12 not good and I know it, but my memory can't do better (
About optimisation the OS and Waza I know, yesterday i tried more time do waza manually but with ocx tweaker it was little faster )

[Raja@ASUS]

If none of the above works (timings/freq combinations and voltage) and DIMMs are at max every which way then the only place you have to go is the OS (fresh stripped install, correct setup, optimised maxmem and waza). Only thing with that; the increased IO will hit the DIMMs too so it can be tricky.

[K404]

tRAS= should be tRCD+CAS+tRTP.

IMO that's too cut n dried. I've found plenty of examples over the years where IC density has dictated that tRAS has to be increased for stability before any other primary timing.... but too much takes the stability away again.

(assuming the user doesn't want to increase any voltages further)

[Raja@ASUS]

IMO that's too cut n dried. I've found plenty of examples over the years where IC density has dictated that tRAS has to be increased for stability before any other primary timing.... but too much takes the stability away again.

(assuming the user doesn't want to increase any voltages further)

tRAS merely alerts for the next row activate to the same bank - a page close. And "too much" should have no negative impact on stability unless one has mismatched tRC. What I provided above is the optimum for a page close scenario.

The rest of the performance impact and gains come down to the scheduling and reordering capabilities of the chipset and the corresponding IO capabilities of the DIMMs. On these architectures (and I do believe we are talking about IB in this thread at least), CAS takes general precedence over tRAS as there will be far fewer page misses than column reads The re-orderng here is a lot more efficient than what we have known in the past.


When a user is tapped out for CAS, then the only option is to start looking into the lesser timings.

[Splave]

tRAS merely alerts for the next row activate to the same bank - a page close. And "too much" should have no negative impact on stability unless one has mismatched tRC. What I provided above is the optimum for a page close scenario.

The rest of the performance impact and gains come down to the scheduling and reordering capabilities of the chipset and the corresponding IO capabilities of the DIMMs. On these architectures (and I do believe we are talking about IB in this thread at least), CAS takes general precedence over tRAS as there will be far fewer page misses than column reads The re-orderng here is a lot more efficient than what we have known in the past.


When a user is tapped out for CAS, then the only option is to start looking into the lesser timings.

so there is a point where lowering subtimings that you will actually be slower? because it will just disregard the value that you entered if it is too low?

[Raja@ASUS]

so there is a point where lowering subtimings that you will actually be slower? because it will just disregard the value that you entered if it is too low?

Depends what Intel do at the IMC end, the chipset will have to issue the correct spacing. Whether or not that adds a larger delay you guys will have to test. Most of the timings are 4 clock limited due to the length of a burst and will revert to that even though the register set allows lower numbers to be inputted (internally these will = 4). Depending on the vendor, the timing ranges can be different (1 may = 4 and 2 = 5 instead of 4=4 and 1,2,3 just reverting to 4). When the DQ lines are toggling, you cannot send certain commands to the same bank.

[Splave]

^thanks

[Raja@ASUS]

^thanks

Quick list for you to reference if you are interested, it's nice to see you guys exploring these things.

1) All same rank (SR) read to read and read to write delays are limited to 4 clock spacing internally due to burst length. Write to read and read to read DD may go lower depending upon how much IO the DIMMs and chipset can handle with the minimum spacing limited due to issues with crosstalk during a burst.


2) tRAS can go to tRCD+CAS+2 on some DIMMs. This is likely possible when there is a burst chop (not to be confused with number 1 above), which is still four clocks in length but with two clocks masked. I have seen no adverse effects of setting tRAS this low on DIMMs that can do it. If tRAS is set lower than this, you will need to see if the chipset auto spaces to four instead of a possible two where permissible - and adjust to CAS+tRCD+2 manually to prevent performance loss.



3) tFAW minimum is 16, as tRRD is internally limited to 4. Setting it lower should revert to 4 depending upon how BIOS is setup. As a rule setting some spacing here (2-6 clocks over the tRRD X 4 value) is preferable to setting tRRD higher because tFAW is only enforced after four consecutive ACT requests to the same rank, where as tRRD is the spacing between each ACT.

tFAW was introduced to save DRAM power without having a huge impact on performance. Latching a row accounts for a majority of DRAM power consumption hence why this timing was introduced. Most DRAM is designed with some tFAW spacing in mind, so being able to run tFAW at its minimum value is very much limited to high performance low latency kits.

Some of the other stuff I will have a look at time permitting and update guides as required with info.

-Raja

[C-N]

@ Raja, good to see someone spelling things out for the layman such as myself.

Out of curiosity are you the Anandtech/DFI Raja?

[C-N]

Update

C-N - 6:24:359 - 48x104.17 - 1250MHz - 8-10-8-24-90-1 - Gigabyte UD5H - GSkill C8 2133mhz 2x2GB/BBSE - 1.86v - Stock Air

VDimm & VCore is higher than it needs to be & sorry I botched the CPU-Z board tab but its the UD5H as AIDA64 shows & she's on bios F8c

[dinos22]

nice one CN

[ZenEffect]

sweet run C-N, the read bandwidth in aida64 is really really good

i love messed up screen shots! it means your adrenaline was going watching the loops... and you get too excited taking the screen shot in fear the system would crash out. THAT is benching fun at its finest.

fun 1 seriousness 0

[M.Beier]

Thought it was a shame for FUGGER the legend to have the poorest submission in the thread, so beating him by miles!
My gaming OS, unplugged my ram and mounted the GTX3... IMC on this CPU doesnt allow anything, Im jinxed! So.... Once I get a real CPU that is capable of running ram at acceptable speed, I'll swap to tweaked XP, but for now, here is something to giggle of

M.Beier - 06:37:291 - 50 x 100 - 1200.00 - 9-11-9-27 - Extreme6 - GTX3 PSC - 1.65 - Water/Air

EDIT;
And yes, you are right, nothing is tweaked, not realtime, no nothing
This OS has been through P67 w. 2600K, Z68 w. 2700K, Z77 w. 3770K

*Did close steam though.

[ZenEffect]

i dont see charles blaming the imc for his score.

[Dumo]

This thread is amazing

[OC Nub]

Got a long way to go but getting better.

OC Nub- 6:24.078-47x106.3- G.Skill 2x2gb F3-17066cl7PIS @1275mhz-8-12-8-27-1T 1.88v- Maximus 5 Gene- SS