Very interesting, tested and confirmed this myself and for this CPU Im finding bclk 130-133 to be optimal. For example, dropping to 100.00 x 50 requires 0.045v more on vcore for stability than 131.6 x 38.

Are all CPUs going to be totally different for optimal bclk or is a 130-133 range going to be optimal for several CPUs? I would try for myself but I only have 1 CPU here right now.

Quote Originally Posted by Raja@ASUS View Post
Assuming there are no major differences in memory frequency, it is entirely possible that asking the internal PLL for a greater level of multiplication of the reference clock produces more phase error or increases jitter. If that were to be the case, increasing Vcore and tuning the voltage of any other related bus becomes necessary to counter any loss in sampling margin (may not always be successful either).