AMD FX-8150 Bulldozer finally tested

[dess]

Well, BD is very similar to Prescott in many ways, it is very very sensitive to the code quality, due to the fact that each thread of a core only have 2 large decoder, the front end is very limited, and you have to wait for more decode steps to feed your out of order more parallelism opportunity.

So you say AMD lied when they've presented BD's uarch with one 4-way decoder in the frontend, and it's really two 2-way ones in the integer clusters? And so there is also an x-way one in the FPU, or what?

Or, are you speaking about that while peak IPC/thread = peak IPC/core with SMT, it's (peak IPC/module)/2 per thread with CMT? Well, that I've also pointed out earlier in this (edit: the other) topic, and asked what could be the rationale behind it.

Anyway, I think the peak IPC is really 3.0/thread here (normal integer x86/x64 instructions wise), because of code-fusion Opteron146 has mentioned already.

the most sophisticated bench suites are on Toms Hardware and HT4u, toms because it test video edeting and compiler performance

Too bad some of Tom's tests are flawed.

BTW, five more to include, if you will: TechSpot, Legion Hardware, Hi Tech Legion, oZeros, VR-Zone.