AMD Zambezi news, info, fans !

[demonkevy666]

I wouldn't bother launching it if this was the case. They (reviews) will generate a lot of negative buzz even if the mythological "fix" eventually arrives.

how do we know pre-caching is working or not ?

correction Prefetch, or is it trace cache. all i know after reading is it's 8Kbyes for the module and 4Kbytes to each core. -__-

i am so lost on bulldozers lol

[Opteron146]

correction Prefetch, or is it trace cache. all i know after reading is it's 8Kbyes for the module and 4Kbytes to each core. -__-

i am so lost on bulldozers lol

You maybe mean the write (combining) buffer to the L2 which is needed because the L1 is write through?

[demonkevy666]

You maybe mean the write (combining) buffer to the L2 which is needed because the L1 is write through?

i spent most the day looking for it yesterday it was trace cache.
even sandy bridge using something similar

[dess]

i spent most the day looking for it yesterday it was trace cache.
even sandy bridge using something similar

Then keep looking as it's called write coalescing cache.
The other one is related to the instruction cache (instead of data cache).

[memmem]

What I can´t understand from an engineering stand point:

FX-8150: 294mm²
i7 2600K: 216mm² with IGP

Of corse we don´t know the transistor count in FX-8150 or the density of Globalfoundries process, but still is a major difference in die size for less overall performance (assuming the leaks are from a final plataform).

May XOP and FMA4 be responsible for this die size?

[Brice MJ]

What I can´t understand from an engineering stand point:

FX-8150: 294mm²
i7 2600K: 216mm² with IGP

http://www.hardwarebenchnews.com/wp-...r_Die_size.png

315mm²