AMD Zambezi news, info, fans !

[flyck]

Me too.


I would think it is clocked much higher than the rest of the L2. The higher the L1 throughput is the less it holds back execution. So, L1 accesses needs to be as fast as reasonably possible. The ~22 GB/s of (apparent) L1 Write is roughly 1/6 only of the ~130 GB/s of L1 Read... So, you can store the results of a computation 1/6 the speed of reading your datas. True, the amount of initial datas are usually bigger than of the results, but the ratio is not always >= 1:6. There can even be more results than initial datas.

Of course, it all depends on the size of this WCC, as well, so that how often we running out of it. I hope it's reasonably sized. (The rather low number in AIDA64 could also come from that it writes 64KB [size of L1D], while the WCC is certainly lesser.)

It does have a buffer so they are not stuck by the write speed. And the l1 write is correct because you expect it to be in the facinity of the l2cache. However the l2cache speed is just incorrect (wether it is a hardware issue or an Aida64support issue). One would expect the l2cache to reach at least 50-80Gb/s (it should be a higher latency with higher bandwidth construction compared to the current x6 lineup.... but that one has a lower latency, a lower frequency with higher bandwidth.).

These results seem more like a read/write through up to the memory. So either a hardware or an Aida64 software issue.