IPC is just as bad as frequency from a power perspective. ipc cannot be scaled up without huge power drawbacks. Both ipc/frequency should have a good relation to have proper performance. If the difference is to big you can expect bad performance. None of those extremes are at work for SB, BD, K8, nehalem, CoreDuo.
Also the write through concept isn't really an issue because the stores should be stored in a buffer and are written out more bandwidth driven (bundled if possible) to have less latency impact. (Whether or not it turns out that way needs to be seen).
it will have an impact if the l2 cache is extremely slow as results above indicate. However Aida64 also reported that Brazos has 0MB/s write on Brazos... so if te tested version doesn't support it properly strange result are common.




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