Quote Originally Posted by drfedja View Post
Of course, but main difference between Bobcat and Bulldozer is that the Bobcat is low power design with high latency, low performance single channel memory controller, much smaller core, less cache and much simpler FPU. I simply can't believe in that the Bobcat per clock is faster than Bulldozer. Maybe, Bulldozer per clock is equal to Atom ?
Well L1 is bigger, and Write Back, not only Write Through. Thus, Bobcat has a clear advantage there. AFAIK, sPi is quite cache depended, maybe that alone is enough for that bench to scale a bit better @bobcat.

Quote Originally Posted by Oliverda View Post
What is the difference?
Nobody knows, but higher version numbers are always better. Someone with a BD CPU has to grab an AsRock board now and make some comparisons, or wait for his board for (beta) BIOS updates.

Quote Originally Posted by drfedja View Post
In pipelined archiceture who cares if instruction has 4 or 6 cycles latency. Pipeline miss-predict has 15-16 cycles of penalty, so if instruction latency is lower than that, that is not problem if code isn't too brancy. Problem is only FDIV latency, but how much often is usage of FDIV.... very low. Overall high latency FDIV can't affect on performance.
As usual, the fun thing with BD is its FlexFPU. In the FDIV case, both FMAC pipes can calculate a FDIV µOp, thus you have double throughput. Even latency might be better. If there are lot of FDIVs, two FDIV µOps can be scheduled simultaneously ;-)
That is probably the reason why somebody wrote some pages before, that FDIV is "faster" on BD ;-)