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[Megacharge]

what's "super pi" again?

It's Lemon Meringue.

[JF-AMD]

I no understand this:

Attachment 120169

Same result with different frecuency?

some options are: one is fake, both are fake. either option is probable

i hate finding posts like this
smartidiot89 posted this at amdzone

Then why do you keep reading it and posting it on multiple sites. Based on his comment that amd doesn't know when it is launching, I tend to believe it is not true.

[informal]

Just for kicks : Bobcat's performance in superpi and wprime. This is a mind experiment since bobcat can't reach this clock,but bulldozer can be clocked down to 1.6Ghz.
1.6Ghz Bobcat in super pi gets a score of 49s => 4.2Ghz should get ~18.7s
1.6Ghz Bobcat in wprime (2 thread/cores) gets a score of 72.1s => 4.2Ghz should get ~55s in single core test

So 4.2Ghz Bulldozer core which in single thread workload such as super pi has 128bit fmac on its disposal is slower than Bobcat @ 4.2Ghz by 6% and in wprime is faster by 6%. Bobcat has 64bit FPU. It does look weird. So even if someone has a hardware that posts those scores (real hardware,not faking benchmarks),it may not be final platform.

[Pestilence]

Who cares about stupid super pi. It has zero bearing on anything.

*edit* hmm a little ironic post I guess given my current avatar.

I thought super pi was a benchmark that showed single threaded performance.

[Nintendork]

It shows nothing as it's based on ancient coding.

For "pi" wprime is more up to today's standard.

Single thread performance? good joke.

We know how much A64 beat P4 on IPC but it lose in superpi

[radaja]

Then why do you keep reading it and posting it on multiple sites. Based on his comment that amd doesn't know when it is launching, I tend to believe it is not true.

what?

[Dumo]

This thread is getting nowhere

Peeps fighting and arguing over benchmarks from "half baked BO whatever ES" and "probly final rev.ES before retail" chips...This is not cool

Getting bored with SB and exited to find new chip to overclock, but this is such a turn off. Lol

[Sparky]

I thought super pi was a benchmark that showed single threaded performance.

If all you want to do is calculate pi all day then it might have some bearing, but it is probably the furthest from measuring any real world performance. Totally useless.

Trust me, this was beaten to death years ago

[drfedja]

It shows nothing as it's based on ancient coding.

Of course not, but if multiple benchmarks are slower on average 25-35%, that's tells us that something is wrong, or the marchitecture is flop.

For "pi" wprime is more up to today's standard.

wprime is more integer than float and uses numerical method to calculate square root. So, it measures integer multithread performance, not FP.

Just for kicks : Bobcat's performance in superpi and wprime. This is a mind experiment since bobcat can't reach this clock,but bulldozer can be clocked down to 1.6Ghz.
1.6Ghz Bobcat in super pi gets a score of 49s => 4.2Ghz should get ~18.7s
1.6Ghz Bobcat in wprime (2 thread/cores) gets a score of 72.1s => 4.2Ghz should get ~55s in single core test

So 4.2Ghz Bulldozer core which in single thread workload such as super pi has 128bit fmac on its disposal is slower than Bobcat @ 4.2Ghz by 6% and in wprime is faster by 6%. Bobcat has 64bit FPU. It does look weird. So even if someone has a hardware that posts those scores (real hardware,not faking benchmarks),it may not be final platform.

Interesting comparison. There isn't chance for BD to be slower per clock than Bobcat.

[Opteron146]

Interesting comparison. There isn't chance for BD to be slower per clock than Bobcat.

Nobody knows why intel's since Yonah's times are better than a K8 or K10, Yonah was generally not faster than a K8 either. So we don't know anything, hence why shouldn't be Bobcat faster? Anyhow, it is another design, and the important thing is that Bobcat won't hit 4.2 GHz, however, BD will.

Comparisons at the same clock are interesting from a theoretical point of view - but not practical.

[drfedja]

Of course, but main difference between Bobcat and Bulldozer is that the Bobcat is low power design with high latency, low performance single channel memory controller, much smaller core, less cache and much simpler FPU. I simply can't believe in that the Bobcat per clock is faster than Bulldozer. Maybe, Bulldozer per clock is equal to Atom ?

[Olivon]

what?

He said end of the NDA has a date : October 13

[Oliverda]

AGESA 0.0.9.2 or 1.1.0.0?

What is the difference?

[m411b]

If all you want to do is calculate pi all day then it might have some bearing, but it is probably the furthest from measuring any real world performance. Totally useless.

Trust me, this was beaten to death years ago

Yes, yes it was!

[muziqaz]

What is the difference?

Updated CPU code, features being used properly?

[FlanK3r]

why do u think it ?

[muziqaz]

why do u think it ?

Who are you asking? Me?
If yes, then I am basing this on my own experience. I remember with 1st Phenom IIs we had some RAM compatibility problems, and with every updated AGESA code in new BIOS release we would get better and larger compatibility list and higher NB clocks would be possible and CPU would be less resistant to various performance tweaks. I am not saying that this is how it works, just extrapolating from my own observations.

[Pestilence]

what?

Just ignore his comments as they're not even worth reading anymore. Until he posts something concrete he's pretty much just a ghost.

If all you want to do is calculate pi all day then it might have some bearing, but it is probably the furthest from measuring any real world performance. Totally useless.

Trust me, this was beaten to death years ago

Thanks sparky.

[informal]

Interesting comparison. There isn't chance for BD to be slower per clock than Bobcat.

Actually it is possible but unlikely . If it happens it may be due to latencies of certain fp instructions.

[AbortRetryFail?]

I thought super pi was a benchmark that showed single threaded performance.

In a 486DX processor ...

[drfedja]

Actually it is possible but unlikely . If it happens it may be due to latencies of certain fp instructions.

In pipelined archiceture who cares if instruction has 4 or 6 cycles latency. Pipeline miss-predict has 15-16 cycles of penalty, so if instruction latency is lower than that, that is not problem if code isn't too brancy. Problem is only FDIV latency, but how much often is usage of FDIV.... very low. Overall high latency FDIV can't affect on performance.

[Pestilence]

He said end of the NDA has a date : October 13

THAT long from now? Jesus.

[informal]

For most of those benchmarks,regardless if they are real or fake, the key thing is SIMD performance. Integer SIMD is handled also by the new FPU inside bulldozer. So this will be the key for good or bad reviews. If it doesn't beat K10 in single thread or poorly thread integer SIMD workloads,it may not get so favorable reviews. If it manages to do this it will be both faster and more efficient than K10,in both single thread and multi thread benchmarks. Now,how all these "leaks" correlate to real performance is anybody's guess. At least in single thread workloads,when both halves of the flexfp are working on one thread,Bulldozer should be faster than K10 at similar clock. We don't see this in any of the leaks. It is actually slower by 15-20%,which goes against what we know about its FPU.

[Opteron146]

Of course, but main difference between Bobcat and Bulldozer is that the Bobcat is low power design with high latency, low performance single channel memory controller, much smaller core, less cache and much simpler FPU. I simply can't believe in that the Bobcat per clock is faster than Bulldozer. Maybe, Bulldozer per clock is equal to Atom ?

Well L1 is bigger, and Write Back, not only Write Through. Thus, Bobcat has a clear advantage there. AFAIK, sPi is quite cache depended, maybe that alone is enough for that bench to scale a bit better @bobcat.

What is the difference?

Nobody knows, but higher version numbers are always better. Someone with a BD CPU has to grab an AsRock board now and make some comparisons, or wait for his board for (beta) BIOS updates.

In pipelined archiceture who cares if instruction has 4 or 6 cycles latency. Pipeline miss-predict has 15-16 cycles of penalty, so if instruction latency is lower than that, that is not problem if code isn't too brancy. Problem is only FDIV latency, but how much often is usage of FDIV.... very low. Overall high latency FDIV can't affect on performance.

As usual, the fun thing with BD is its FlexFPU. In the FDIV case, both FMAC pipes can calculate a FDIV µOp, thus you have double throughput. Even latency might be better. If there are lot of FDIVs, two FDIV µOps can be scheduled simultaneously ;-)
That is probably the reason why somebody wrote some pages before, that FDIV is "faster" on BD ;-)

[dess]

I thought super pi was a benchmark that showed single threaded performance.

AFAIK SuperPi is from the 90's, and use old x87 instructions and registers which are obsolete already, not used since almost a decade, being not as efficient as newer FPU instructions and registers. Modern CPUs support them only for backwards compatibility.