Quote Originally Posted by informal View Post
Actually it is possible but unlikely . If it happens it may be due to latencies of certain fp instructions.
In pipelined archiceture who cares if instruction has 4 or 6 cycles latency. Pipeline miss-predict has 15-16 cycles of penalty, so if instruction latency is lower than that, that is not problem if code isn't too brancy. Problem is only FDIV latency, but how much often is usage of FDIV.... very low. Overall high latency FDIV can't affect on performance.