AMD Zambezi news, info, fans !

[PolRoger]

Saw on youtube.....5.89Ghz 8c/8t @ 1.63Vcore SS -30C idle stable....nice

Link?

Now if it will only do WPrime 1024M stable and more curiously how will it compare to a 2600K 4c/8t @ ~ 5.8Ghz+ under similar cooling?


I'm looking forward to more info being released in the days ahead!


Oh and a little off topic but while I'm posting... congrats chew!

[Oese]

WCC is a joke in the current BD implementation and is not able to catch up with the massive loss that comes from the L1D. The entire caching-system is lowering the performance of the µarch. The L3 is a non-inclusive victim cache (L2 data are evicted to the L3) with data transfered from L3 to the L1D of the expected core without being copied to the L2. That mean high snoop traffic in order to keep the coherency correct. And snoop traffic is something really unwanted from a bandwidth/performance pov. There is a pardox here : The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

Interesting reads here, but 3 questions:

1.) why would AMD do such a thing (you wrote for better clock-scaling, that means higher clocks or better scaling?)

2.) can it be optimized further

3.)

Write Trough means that every write to the cache causes a synchronous write to the backing store. Because L2 is slower than L1, L1 must wait for L2 to write out data.

this contradicts somewhat

The L3 is a non-inclusive victim cache (L2 data are evicted to the L3) with data transfered from L3 to the L1D of the expected core without being copied to the L2.

or you mean this can be due to WCC? I am not a professional, but I would guess WCC doesnt take that long to preserve coherence... If anything at all, I'd guess the waiting of L1D for L2 can be a problem, but if stuff is written to L1D fast, and then some cycles later WCC writes to L2, I guess there will only be rare cases where

The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

really matters...

I guess

data transfered from L3 to the L1D of the expected core without being copied to the L2.

will first speed up things, then

snoop traffic in order to keep the coherency correct

will need some time. All, to my eyes, depends on how this stuff is used, it can be faster in one case, and slow in the other... Mhm somewhere we came to that conclusion before

Maybe the problem is because of

The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

, one core might need to wait for WCC to complete to ensure coherency?

Ahhhh btw... CONGRATZ FOR NEW WR

[mR Yellow]

When will the first reviews come out?

[drfedja]

WCC is a joke in the current BD implementation and is not able to catch up with the massive loss that comes from the L1D. The entire caching-system is lowering the performance of the µarch.

How you can claim such things ? Are you chip architect of BD, or some experienced with low level code optimisation programmer to claim that the WCC is a joke or good enough patch for WT policy?

The L3 is a non-inclusive victim cache (L2 data are evicted to the L3)

So, on 10h is also non-inclusive, or exclusive, and K10 with L3 cache is faster than K10 without cache. Gain from such large L3 may be bigger if cache is faster, but K10 core run very well withot L3. Non-inclusive L3 isn't reason for low performance, especially in FP intensive, or integer intensive, number crunching apps like wprime or CB. With BD module there is 2MB of 16-way L2 cache which is enough for achieving acceptable performance levels. I don't think so that the SB will run so great without L3 cache. I also think that cache hieararchy of AMD K10 and BD is some kind of tradeoff for having good enough performance of low end, and APU products, like Llano and Trinity.

with data transfered from L3 to the L1D of the expected core without being copied to the L2. That mean high snoop traffic in order to keep the coherency correct. And snoop traffic is something really unwanted from a bandwidth/performance pov. There is a pardox here : The L1 is in Write-through, but you're not sure a data not in L2 is not the L1D of another core.

L2 is mostly inclusive of L1D caches, so the data from L1D caches in most cases is in L2, because of WT and mostly inclusive cache policy. But to have complete picture of the puzzle, we need to know how they solved problems with snoop traffic and how much from for eg. core 0 must snoop core 1 L1D through the L3.
The question for AMD is what is the average hit rate of L1 copy in L2.

[drfedja]

If anything at all, I'd guess the waiting of L1D for L2 can be a problem, but if stuff is written to L1D fast, and then some cycles later WCC writes to L2, I guess there will only be rare cases where really matters...

I told that before. For WB cache in opposite from WT, writes are not immediately mirrored to the store.

From RWT Article about BD architecture:

Stores from both L1D caches go through the WCC, where they are buffered and coalesced. The purpose of the WCC is to reduce the number of writes to the L2 cache, by taking advantage of both spatial and temporal locality between stores. For example, a memcpy() routine might clear a cache line with four 128-bit stores, the WCC would coalesce these stores together and only write out once to the L2 cache.

[hiwa]

I would not go as far as to say cherry picked. I blind pulled with no windows testing 24 chips based on there VID, the 4th chip we tested (note not a pretested ever chip ) did 8.4

We still had twenty chips left to try out but really didn't care after the 4th one.......

that's amazing man, that mean we will see + 8.4 chips too for sure.

[Lanek]

When will the first reviews come out?

When the cpu will be launched, rumors point mid october now .. well not for tomorrow for sure.

[FlanK3r]

Chew*, happy testing others chips , nice hand choice for 4th 8.4GHz+ chip! Only this 4th was the first!

[Lmui]

If that's just four chips, I want to see the best chip of a batch. I'm pretty sure that hitting 8.6+ in the first two to three weeks after launch won't be hard and with time, breaking 9 should be possible.

ing awesome achievement guys.

[maltrabob]

the only catch is that AMD dosnt do marketing and we all know that

Well, if they don`t do marketing, who planned today`s surprise for them? On Intel`s day as well ;-).

[Dumo]

Link?

Now if it will only do WPrime 1024M stable and more curiously how will it compare to a 2600K 4c/8t @ ~ 5.8Ghz+ under similar cooling?


I'm looking forward to more info being released in the days ahead!


Oh and a little off topic but while I'm posting... congrats chew!

http://www.youtube.com/watch?v=5AB-G...layer_embedded

Even if an FX8150 needs to go 6.5Ghz to compete with 5.8Ghz 2600K in 3Ds...it still better considering how easy to find 58X 2600K

[FlanK3r]

but...its speculation still...Maybe not!

matla:oh, I forgot at Intel day , today is FX suprised OC day

[informal]

Ok guys,clock speed is great and all but don't expect too much from FX (versus i7 or even thuban). That way you won't be that much disappointed. ..

[drfedja]

Ok guys,clock speed is great and all but don't expect too much from FX (versus i7 or even thuban).

AMD says up to 35% better performance from previous generation.

That way you won't be that much disappointed. ..

You are now restrained optimist ?

[Manicdan]

AMD says up to 35% better performance from previous generation.
You are now restrained optimist ?

thats for server, so its already going to have 33% more cores, if they are clocked an higher that means IPC went down, but if they are lower clocked thats great news.
but i think informal is just playing it safe.

[Dimitriman]

AMD says up to 35% better performance from previous generation.
You are now restrained optimist ?

I feel bad for Informal really, hes been on this case since day 1 with full focus and optimism but the latest leaks have broken his spirit (and mine kinda). It's sad really, but like he said, better to be positively surprised than having too high expectations.

[Megacharge]

AMD says up to 35% better performance from previous generation.
You are now restrained optimist ?

it's because of that "Bulldozer engineer" xsecret. He's got us convinced it's a 4 core netburst with hyperthreading. So we have no choice but to expect it to be crap and hope for the best because he helped create that chip so he knows best.

[tifosi]

http://valid.canardpc.com/show_oc.php?id=1874555

i'm sorry for being OT, but does the above link indicate a processor oc'ing all its 6 cores to 7+ Ghz? I don't think so. I think it is mostly the fact that CPU-Z has all information and is showing all the information, i.e number of cores etc.

On topic, let us hope that BD has more to it than just clocks. When informal and all are losing hope, i wonder what remains for me...

[Oese]

mhm informal by what you write in your blog, even if ipc per bulldozer core will not or even slightly be higher then per thuban core, I think this processor gonna rock (dont care much if its slower the i7 on stock clocks given that OC numbers )

only question mark is at power consumption still.. though the shared design and clock gating should do its work..

hehe maybe we will thank xsecret one day, when we were all laying down depressed and then really the boom boom bulldozer breaks in with thuban ipc or more and 5ghz on air

[repman]

thats for server, so its already going to have 33% more cores, if they are clocked an higher that means IPC went down, but if they are lower clocked thats great news.
but i think informal is just playing it safe.

I think they are clocked lower (Compared to MC).

If we compare BD (Zambezi) to Phenom II: it has much much higher clock potential (for future CPU's, and it's design is something they can work on), and IPC should be higher. So going by that it shouldn't be a bad CPU.

[drfedja]

thats for server, so its already going to have 33% more cores, if they are clocked an higher that means IPC went down, but if they are lower clocked thats great news.

If that is true, BD per core is faster than K10. BD-Interlagos Opterons is almost same clocked as Magny Cours. How much is 12-core Opteron faster than 8-core? For 50% more cores, 35% or something like that? There is no chance that Zambezi could be slower on average than Thuban.

but i think informal is just playing it safe.

I know!

[maltrabob]

only question mark is at power consumption still.. though the shared design and clock gating should do its work..

That`s what I am curious to know as well. But since FX-8150 is stated to be a 125W one, it should be pretty ok considering it`s eight-core (or four-module).

[xsecret]

http://valid.canardpc.com/show_oc.php?id=1874555

i'm sorry for being OT, but does the above link indicate a processor oc'ing all its 6 cores to 7+ Ghz? I don't think so. I think it is mostly the fact that CPU-Z has all information and is showing all the information, i.e number of cores etc.

On topic, let us hope that BD has more to it than just clocks. When informal and all are losing hope, i wonder what remains for me...

That's the record with 6 active core and HT enabled.

[Oese]

yes, 3.6ghz/4.2ghz turbo 8core in 125W TDP seems not too bad... especially if these ipc numbers hold true.

BTW post no. 1000 time for an avatar

[2good4you]

If I remember correct the first 8 samples tested did 8Ghz or more with LN2, also some very high on water. Clocks is good, and architecture is...

Like another said, "some" guys without mension any in here may be just great pay'd off by Intel who don't know whay they're talking about or have too much spare time. In here BD is kind of underestimated from guys who does'nt know. Even with an eventuelly game from AMD (ohh can it be?), they buy it like a child. Wait for release... It will not perform bad, but compared to whay you've wait and see.