AMD Bulldozer to be launched in 19th September

[drfedja]

ILP isn't at all dependent on the number of ALUs. Having more ALUs, and a smart front end, only allows you to take advantage of ILP when present and convert it into IPC, but the ILP is fixed.

Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible.
ILP is dependent of course by smart front end, and also by memory ordering subsystem. CPU with good memory disambiguation will have more ILP than CPU without it.
When I talk about memory level paralelism I mean that how CPU handle load/store operations. This is one of main CPU function (load and store). ILP and IPC are different words for same think. Only difference is how it is measured. IPC measures how much instructions are executed per cycle. ILP is not measure. ILP is feature - for example: how many instructions is executed per minute, second or cycle is feature of instruction throughput.

ILP depends on the specific code being executed. Instructions that depend on the results of previous instructions reduce ILP. Some pieces of code don't have any ILP and only clocks or speculative execution can help.

ILP and IPC depends on specific code. Instructions can't depend on previous instruction, data has dependencies. If n-th instruction uses data which is calculated by n-1 instruction, that instruction works with data which has data depenedent by previous calculated data. Because of data dependencies instructions must wait on scheduler for needed data.
Speculative memory address calculation can help with data dependencies.