Quote Originally Posted by informal View Post
Solus Corvus already corrected you(after I did even before that). You need to read that blog post again.The whole point of co-processor model is that one core can have the whole FPU(2xFMAC) in case of second core having no fp instructions scheduled.Yes ,even in legacy code and that's the beauty of AMD's approach.:
Theoretically you are right, one core (Single thread) can issue, execute, result 4 micro-ops meaning it could use all the FP pipes (2x FMACs + 2x MMX). But i find it very hard if it could sustain it in real world usage.