Quote Originally Posted by -Boris- View Post
Seems like L1 and L2 will have a bit higher latencies. :/
These latencies were known for a while now.

More interesting are other tidbits like:
  • 15 or 20 cycle branch prediction penalty
  • integer muls only issueable every 2 (32 bit) or 4 (64 bit) cycles -> multiplier running at slower clock or simply not pipelined anymore?
  • module/cores have a slow and a fast mode (accelerated mode?) -> twice the int core clock?
  • module is called compute unit
  • FMA, FADD, FMUL latency 5 cycles (while other table states 6)

etc

I'll cover that on my blog soon.