[FW]Llano / Bulldozer ES ???

[XRL8]

As for the copyright date.I think its the time packaging has been finalized for the cpu die.
All phenoms II X4 have 2008, even the 970 one.
All phenoms II X6 (that i have seen around the web) have 2009.
Cpus production date doesnt have anything to do with date on the copyright.And its logical ,because its about the packaging with stays the same.
And just because it looks similar going from athlon 64 up to bd,it doesnt mean its the same.It cant.
So 2010 seems most probable, as that is the year they finalized the design.

[informal]

MaximumPC has a video on how AM3+ CPUs can work in AM3 socket.
http://www.maximumpc.com/article/new...er_we_find_out

[XRL8]

That guy told absolutely nothing using 2m32s of my life."we will know when they launch"

[informal]

Well actually he said that maybe some of the motherboard manufacturers knew the BD electrical specifications and built them into their AM3 boards after certain revision.

[undone]

Everybody look at this one!

[XRL8]

Yeah, he said "maybe".And didnt we knew this already once asus broke the news ?Thats the same speculation.Maybe they did what they should be doing on all boards ,like kink said.
And maybe thats a coincidence , or maybe they knew specs for some time, or maybe ...
If that would be true, why werent they sold from the beginning as am3+ compatible ?
We still dont know as far as i see it.Beside the fact that all this talk from AMD about "being unable" was just that.Talk.

[Mats]

Everybody look at this one!

So what? CPU-Z used on an unsupported Fusion A. Who cares?

[FlanK3r]

i think my x6 1055t also says 2008

think or know? This is very old (one from first retails) 1055

[-Boris-]

As for the copyright date.I think its the time packaging has been finalized for the cpu die.
All phenoms II X4 have 2008, even the 970 one.
All phenoms II X6 (that i have seen around the web) have 2009.
Cpus production date doesnt have anything to do with date on the copyright.And its logical ,because its about the packaging with stays the same.
And just because it looks similar going from athlon 64 up to bd,it doesnt mean its the same.It cant.
So 2010 seems most probable, as that is the year they finalized the design.

I see no reason why they would copyright the packaging. Why is it so hard to believe that it's simply the CPU design?

[ajaidev]

Now i dont remember exactly but all the engineering sample i had from Intel always carry a year mark on them with something like "Intel confidential" written on it. Maybe AMD has started putting year marks in their eng samples also.

EDIT: Ohhh ya i remember my sandy bridge sample had 09 year mark written on it where as the processors went on sale in Q3-Q4 2010....

[XRL8]

I see no reason why they would copyright the packaging. Why is it so hard to believe that it's simply the CPU design?

if by cpu design you mean actual die, than yes, its highly probable too.
However if by design you mean overall architecture, than no.

[imamage]

Everybody look at this one!

Probably CPU-Z detect it wrongf

[zanzabar]

maybe this is BD

thats the 1st thing i though of when i saw it, its exactly an am3 key so the board makers saying that they only need a bios update is now confirmed if they dont change the pin count when it goes retail.

[-Boris-]

thats the 1st thing i though of when i saw it, its exactly an am3 key so the board makers saying that they only need a bios update is now confirmed if they dont change the pin count when it goes retail.

Something that I have suspected for a while is that the engineering samples has the AM3 pins. And that's why they talk about compability. But AMD might add the extra pin in the retail CPUs. The extra pin might also be for future updates which won't fit in AM3 at all.

[Johnny87au]

lol can it get any more fake?

[zanzabar]

Something that I have suspected for a while is that the engineering samples has the AM3 pins. And that's why they talk about compability. But AMD might add the extra pin in the retail CPUs. The extra pin might also be for future updates which won't fit in AM3 at all.

if the ES dose not have the pint then they wont have data pin there so u could cut and trace the ground to it, and since there are 2-3 grounds right next to it if it shares the other AM grounds thats an easy fix and or u wont even need that since it will be a key pin. but for amd they normally would want to support as much compatibility as they can even if its unofficial

[FlanK3r]

Zanzabar. But this chip has more pins than AMD Thuban core ,-)...Its not only simply BIOS updated.

number of pins at this ES Zambezi CPU is 961-21= 940! Thuban has 938. And not all boards AM3 has electricaly active contacts for all pins, but most of them only 938 (for Denebs and Thubans)!

AM3+ is 942, think is pins reserve for refresh Zambezi to Komodo

[qcmadness]

Programming guide for Bulldozer arch.

http://support.amd.com/us/Processor_TechDocs/47414.pdf

Contains some interesting facts of the arch.

[-Boris-]

Programming guide for Bulldozer arch.

http://support.amd.com/us/Processor_TechDocs/47414.pdf

Contains some interesting facts of the arch.

Seems like L1 and L2 will have a bit higher latencies. :/

[madcho]

1.6.6 Notable Performance Improvements
Several enhancements to the AMD64 architecture have resulted in significant performance
improvements in AMD Family 15h processors, including:
• Improved performance of shuffle instructions
• Improved data transfer between floating-point registers and general purpose registers
• Improved floating-point register to floating-point register moves
• Optimization of repeated move instructions
• More efficient PUSH/POP stack operations
• 1-Gbyte paging
These are discussed in the following paragraphs and elsewhere in this document.

nice.

[Nikolasz]

I wonder (i ask) is in those chips, is one fpu unit or multiple fpu units as fpu per core?
Im wiling to put some ideas for fpu unit.

[qcmadness]

I wonder (i ask) is in those chips, is one fpu unit or multiple fpu units as fpu per core?
Im wiling to put some ideas for fpu unit.

2 128-bit FMA-type FPUs shared between 2 cores.

[Nikolasz]

Ok , i found that info on amd site
Shure, i want amd to really go beyond intel.


There is fpu solution in web sites, solution that gain 50%-70% better performance then we have it nowdays(cant remember, how many exact % but it was alot ! , just to make this debate) .
It all starts back in begining when become fpu as standard.
Guy found out that original code is bad written.
Since no one is willing to put that into cpus.
Make new way from strach maybe it that code can start be used as "sse".
(he got his own moded sourse code) this code unused, just waiting. For some one smart enugh to start to use it.

Sorry, i got no links, but if someone is interesting ,pm me, i will find it. (or you may find your self, ask this guy what can be done)

[Dresdenboy]

Seems like L1 and L2 will have a bit higher latencies. :/

These latencies were known for a while now.

More interesting are other tidbits like:

• 15 or 20 cycle branch prediction penalty
• integer muls only issueable every 2 (32 bit) or 4 (64 bit) cycles -> multiplier running at slower clock or simply not pipelined anymore?
• module/cores have a slow and a fast mode (accelerated mode?) -> twice the int core clock?
• module is called compute unit
• FMA, FADD, FMUL latency 5 cycles (while other table states 6)

etc

I'll cover that on my blog soon.

[FlanK3r]

DB:whats mean in practice?