wow u must be a genius, looks like no1 thought of that before...of course the 12MB of l2 cache for the core2quad Q9550 is slower than todays memory, and then u have the architecture. That lecturing was so not necessary
What we do know is the memory in Zambezi will be something special, not just that its very high density stuff but also very fast. As of what i read earlier the L2 cache will be working in the same speed as each module (3.5GHz?) and also induvidualy together with its designated module. Each module will have its own L3 cache but also be shared between modules, wich inceases the speed and lower latency. The 1.1V L3 cache will be working at 2.4+GHZ with induvidual frequency depending on load. I dont think Zambezi will have no trouble competing in pure memory speed with SB. But as u wrote,
The power gating will very much interesting to hear about with all these states.




of course the 12MB of l2 cache for the core2quad Q9550 is slower than todays memory, and then u have the architecture. That lecturing was so not necessary 


Bookmarks