AMD Bulldozer server info

[JumpingJack]

I'm not sure whether Intel suffers that. The integrated memory controller, HyperTransport-like bus, even the three-layer cache structure all were implemented by AMD first, and Intel later adopted them. One could say the Core 2 architecture was inspired by thinking that lead to Athlon too - a relatively short pipeline and a focus on IPC rather than frequency. In fact, all this lead Tom's Hardware to title their Nehalem review "Architecture by AMD?" ( http://www.tomshardware.co.uk/Intel-...iew-31375.html ).

Uhhhhhggggghhhh, these type of posts... who invents what first.It is really irrelevant, companies will design products to sell products, and they make technical decisions separate from one another for different reasons and arrive at different conditions at different times.

But to make a point.

Intel implemented an IMC in the 386 days with the 386 SL ( http://fury-tech.com/en/tag/history-...croprocessors/ ) there was nothing really invented here, where you put a memory controller is a design choice of the platform.

The hypertransport bus is based on the EV6, which was DEC, Intel bought out DEC in 1998. Did nothing with the IP, AMD popularized the serial point to point nicely in the K8 line.

3 level cache is nothing new, several non-x86 designs employed a 3 level cache hierachy, the first 3 level cache x86 CPU was produced by Intel, http://www.dailytech.com/16MB+of+L3+...rticle2564.htm didn't help much it was still craptastic netburst.

Core 2 was inpsired by continuing from Dothan, Banias, and Yonah, all those were P6 lineage, I doubt much of the design was inspired by K8... they are two completely different architectures.