Guys, been hitting a wall with this 4E error on the LED.
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range
3. Initialize the APIC for P6 class CPU
4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical
Sorry, I dun have any clue as to what this is? Needs more voltage?