The physical layout of the memory chips seems odd... Are all Fermis like this? It would make more sense to me to have 2 banks of 4 chips on the top and right side. Just from a timing and trace route standpoint. Maybe that rouge chip acts more like a L3 cache rather than being attached to the main mem buffer?
Last edited by LexDiamonds; 01-20-2011 at 07:19 AM.
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