The question is if it's important to have MCH Read ODT available in the BIOS with different values?

Yes, it is and it's going to be necessary to try to have it stable at FSB 500MHz.


BIOS Settings:


Code:
*Extreme Tweaker* 
Ai Overclock Tuner               [Manual] 
OC From CPU Level Up             [Auto] 
CPU Ratio Setting                [09.0] 
FSB Strap to North Bridge        [400] 
FSB Frequency                    [469] 
PCIE Frequency                   [100] 

DRAM Frequency                   [DDR2-1250MHz] 
DRAM Command Rate                [2N] 
DRAM CMD Skew on Channal A       [Greyed Out] 
DRAM CMD Skew on Channal B       [Greyed Out] 
DRAM CLK Skew on Channal A       [Auto] 
DRAM CLK Skew on Channal B       [Auto] 

DRAM Timing Control              [Manual] 
 1st Information 
  CAS# Latency                   [5] 	
  RAS# to CAS# Delay             [5] 	
  RAS# PRE Time                  [5] 	
  RAS# ACT Time                  [15] 	
  RAS# to RAS# Delay             [5] 
  REF Cycle Time                 [Auto (52)] 
  WRITE Recovery Time            [12] 	
  READ to PRE Time               [6] 
 2nd Information 
  READ to WRITE Delay (S/D)      [8] 
  WRITE to READ Delay (S)        [6] 
  WRITE to READ Delay (D)        [6] 
  READ to READ Delay (S)         [4] 
  READ to READ Delay (D)         [7] 
  WRITE to WRITE Delay (S)       [4] 
  WRITE to WRITE Delay (D)       [7] 
 3rd Information 
  WRITE to PRE Delay             [23]	
  READ to PRE Delay              [8] 	
  PRE to PRE Delay               [1] 	
  ALL PRE to ACT Delay           [6] 	
  ALL PRE to REF Delay           [6] 
  Refresh Period		 [16120T]

DRAM Static Read Control         [Disabled] 
Ai Clock Twister                 [Lighter] 
Ai Transaction Booster           [06] 		
Pull-in of CHA PH1	         [Disabled]	
Pull-in of CHA PH2	         [Disabled]	
Pull-in of CHA PH3	         [Disabled]	
Pull-in of CHA PH4	         [Disabled]	
Pull-in of CHB PH1	         [Disabled]	
Pull-in of CHB PH2	         [Disabled]	
Pull-in of CHB PH3	         [Disabled]	
Pull-in of CHB PH4	         [Disabled]	
CPU Voltage                      [1.36250v] 
CPU PLL Voltage                  [1.50v] 
North Bridge Voltage             [1.37v] 
DRAM Voltage                     [1.92v] 
FSB Termination Voltage          [1.30v] 
South Bridge Voltage             [1.05v] 
SB 1,5V Voltage                  [1.50v] 
Loadline Calibration             [Disabled] 
CPU GTL Voltage Reference        [0.63x] 
NB GTL Voltage Reference         [0.67x] 
DRAM Controller Voltage REF      [AUTO] 
DRAM Channel A Voltage REF       [AUTO] 
DRAM Channel B Voltage REF       [AUTO] 

CPU LED Selection                [CPU Voltage] 
NB LED Selection                 [North Bridge Voltage] 
SB LED Selection                 [South Bridge Voltage] 
Voltiminder LED                  [Enabled] 

CPU Spread Spectrum              [Disabled] 
PCIE Spred Spectrum              [Disabled] 
Cpu Clock Skew		         [Delay 500ps]
NB Clock Skew		         [Delay 400ps]

*CPU Settings* 

CPU Ratio Settings	         [09.0]
C1E Support	                 [Disabled]
CPU TM Function	                 [Enabled]
Vanderpool Technology            [Disabled]
Execute Disabled Bit	         [Enabled]
Max CPUID Value Limit            [Disabled]


MCH Read ODT 11T







MCH Read ODT 8T






As you can see it's stable with 0.04V lower NB Voltage and MCH Read ODT 11T and it isn't with 8T. Stability improves a lot with longer MCH Read ODT timing at high FSB and we're going to need it if we want to try to have it stable running with FSB 500MHz.

There's also DRAM Read ODT and DRAM Write ODT but I didn't test it yet if it's better with a different value.


All these timings should be added to the BIOS so we can choose the value that we need to have it stable running.