Quote Originally Posted by terramir View Post
WHAT is TLB? and what does RW-Everything mean
anyways your talking about quad barcelona's right?
terramir
TLB bug, affects B1 and B2 stepping Barcelonas (and Phenom I CPU). It's a cache accell lookup table that was incorrect in some way. It would cause systems to hang upon error. So AMD had a quick fix by disabling the TLB (l2/l3 cache lookup?) via the BIOS for B1 and B2 stepping. B3 stepping fixed this, and was not disabled.

Unfortuneately, disabling TLB tanks L2/L3 cache performance, and some apps that were memory heavy (and by relation, cache heavy) saw a sizeable performance hit. So to resolve this, a few users on XS and other forums found ways to disable the "TLB BIOS fix" that AMD used to turn off the buggy TLB B1/B2 CPU. Vista SP1 and onwards forced the same fix via the OS. Linux Kernal 2.6xx-something had another workaround that didn't cause as much of a performance deficit as disablign the TLB, while still being safe from any possibility of a system hang.

The easiest way around the TLB BIOS patch for Windows (Vista SP1 & +) users, was a peice of software called RW-Everything that could access the BIOS/CPU MSR, and disable the TLB fix, live (realtime). And RW-Everything supports external batch operations (can use a saved list of MSR commands ), so it's the easiest to deal with. Since two MSR commands have to be done (well, 4) for ever core. And for 16 cores... that's a lot of typing :p


That's all, in a condensed, and horribly formatted article :p