I think beside manufacturing problem of the card (the hard to find MOS from TI), other probable main reason for the "delay" is AMD trying to squeeze as much performance out of this chip in the driver. Clock i think is already finalized, but getting optimal output out of a "new" mArch from the driver is plenty difficult IMHO, and with this chip, it seems AMD graphic really want to deliver a pretty serious blow against the green camp. The VLIW compiler in the driver has to be reworked seriously to make sure the promised added efficiency going from 5 way-VLIW to 4-way VLIW really materialized in MOST cases.