AMD: 32nm issues fixed

[Manicdan]

moore's law is not everything. transistor performance is still important as i have said previously.

furthermore, using intel's process as evidence that bulk is faster is not correct. drive currents are important but FO4 inverter delays are a much better metric because drive current does not factor in capacitance or voltage which are essential to delay. getting such PMOS drive currents required a lot of doping which can lead to higher dopant fluctuations. gate pitch on intel's 32nm process isnt all that impressive and neither is their SRAM cell size. speed did hurt size imo.

i'm not debating semantics. i am trying to clarify what i am saying because i dont want to look like a jackass. it's starting to look like an SOI v. HKMG argument which is dumbtarded. a problem does not have to be so straight forward. for example: "our process is not fast enough. how can we improve its performance?". that's a problem. SOI may be able to fix it. the problem does not have to be as extreme as gate leakage where functionality is slowly being destroyed.

also HKMG is performance oriented. you can make a functional transistor on 45nm or 32nm with polySi or SiON gate dielectrics. it just would not be impressive. eventually leakage would cause transistors to act like attenuators but that's ways off.

i bolded the only word in this i understand

[AbortRetryFail?]

if intel is using soi for 22nm....they are not doing it for s and giggles. it must still have better advantages than it does negatives.

Some folks throw stuff out (that has been already properly corrected in this thread) without engaging their cerebral processing units ...



Unless, of course, they know *Moore* about it than Mr. Otellini ...

[generics_user]

this slide is incorrect, intel went with gate last

[ajaidev]

Some folks throw stuff out (that has been already properly corrected in this thread) without engaging their cerebral processing units ...

[IMG]http://i716.photobucket.com/albums/ww165/Back_at_the_Ranch/AMD%20Overlords/Intel_SOI-15nm.jpg[/G]

Unless, of course, they know *Moore* about it than Mr. Otellini ...

I did not throw stuff out there SOI has been considered for 22nm and below. The reason for SOI use in 22nm was stated as partial this means it may not be used initially in the 22nm cycle.

The problem is not that Intel can not pull SOI for 22nm but the process reduction and tick tock cycles are linked with it. The last delay in the cycle has already brought about a feeling of haste.

SOI will be used in combination with HKMG and usage will depend upon 22nm process startup, tick tock progress and what show AMD "and others" put on.

[JumpingJack]

this slide is incorrect, intel went with gate last

The slide is correct, replacement metal gate is another way of saying gate last. The way to read the slide is that it lists possible performance enhancing technologies and the nodes most likely to intercept.

http://www.electroiq.com/index/displ...ng-high-k.html

Today, two main integration options remain: gate-first (often referred to as MIPS, metal inserted poly-silicon) and gate-last (also called RMG, replacement metal gate).

[JumpingJack]

moore's law is not everything. transistor performance is still important as i have said previously.

Moore's law is nothing more than an observation of economics driving innovation to achieve one of two things: either reduction in size (costs) or for, the same die size, an increase in complexity (competitive positioning).

But this is clearly a misunderstanding in what I am saying, perhaps I am not saying it clearly enough. My contention is the use of the word 'fix', to fix something implies that that something is broken. Bulk transistor performance has progressed over time steadily, improving with each generation, and generationally this is typically tied to node transistions as new technquies (such as stressors) or materials are introduced at those natural transitions, over time (the moore's law progression). Absolutely, unequivocably, I 110% agree with you ... it is ultimately performance.

However, be it Intel, TSMC, or Samsung, whoever, it is.... each generational introduction of new technology (usually introduced at a Moore's law progression) results in improve transistors on bulk.... if bulk scaling stopped, if transistor performance halted dead in it's track and SOI was the only way to regain that trend then I would agree, it is a fix. But that is not the case.

furthermore, using intel's process as evidence that bulk is faster is not correct. drive currents are important but FO4 inverter delays are a much better metric because drive current does not factor in capacitance or voltage which are essential to delay. getting such PMOS drive currents required a lot of doping which can lead to higher dopant fluctuations. gate pitch on intel's 32nm process isnt all that impressive and neither is their SRAM cell size. speed did hurt size imo.

FO4 (Fan out of 4) delays are a function of the strength of the transistor as well as other factors that are indeed important to overall clocking of functional blocks and logic stages, it is reported and used by circuit designers so I would agree that FO4 is a good metric to use as a comparision. However, in a discussion of SOI, SOI affects transistor performance which is a key component, not the only component, in setting FO4 delay. In determing the benefits of one or the other substrate it is best to use transistor level metrics because the interconnect is not impacted by the substrate. You cannot isolate the benefit or lack thereof by simply comparing FO4 delay.

In reading further I see you need to be careful because what you said above is quite incorrect. Drive currents are indeed defined by voltage and capacitance as well as mobility, I think you mean drive currents do not account for interconnect parasitic capacitance, FO4 delays do, in which case you are right.

Drive current (Ion) can be cast as follows:


Uploaded with ImageShack.us (borrowed from the link I provided in the prior post).

Note the capacitance (gate capacitance) and voltage (potential difference source to gate mitigated by threshold voltage). So much basic understanding of transistor engineering can be understood from this basic equation (even if it does not account for SCE). For example, Mu(eff) is the mobility, which is why stress engineering has become critical and why self-heating in SOI needs to be addressed at the design level, as higher mobility leads to higher drive current, leads to faster transistors. Lower threshold voltage (Vt) increases drive current, leads to higher switching transistors (SOI, for example, can really help here).

Now to your doping of PMOS, PMOS or NMOS requires good doping enigneering, you cannot make a transistor without doping.. but doping is only one of many ways engineer transistors so be it, so long as it is manufacturable who cares. Again back to the equation -- Mu(eff) is modulated by stress -- that is why eSiGe has been used to enhance PMOS, as an example.

i'm not debating semantics. i am trying to clarify what i am saying because i dont want to look like a jackass. it's starting to look like an SOI v. HKMG argument which is dumbtarded. a problem does not have to be so straight forward. for example: "our process is not fast enough. how can we improve its performance?". that's a problem. SOI may be able to fix it. the problem does not have to be as extreme as gate leakage where functionality is slowly being destroyed.

I don't think you look like a jackass, you obviously are knowledgable about the topic.

But we are arguing semantics, in the history of the discussion I simply stated SOI doesn't fix anything, it provides benifical improvements in some aspects and comes with it's own set of headaches. Bulk transistors are obviously not broken, you can't fix something that is not broken.

I agree, the SOI v. HKMG is a dumbtard debate, they are two completely separate things and I am not making that argument/debate. Perhap it was confusing or you did not completely read my post ... I use the HKMG as an example of a tech that does fix something -- gate oxide scaling. That has stopped dead in it's tracks for the obvious reasons you state below, HKMG allows that scaling to resume. SiON cannot go any thinner without giving a craptastic power chomping device, so nobody (except IBM) is doing it. The industry is moving to new gate materials as the fix, Intel cut it in at 45 nm the rest of the industry appears ready to do it at 32 or 28 nm. HKMG notwithstanding, and contrary to this example, bulk relative to SOI has not resulted in a craptastic device (yet) so SOI is not fixing anything. That is sorta my point.

"our process is not fast enough. how can we improve its performance?" Precisely the right question to ask, and since bulk has improved generation after generation, there is nothing broken to fix (except perhaps my record player). SOI is certianly a fascinating technology, but in and of itself is not fixing anything.

also HKMG is performance oriented. you can make a functional transistor on 45nm or 32nm with polySi or SiON gate dielectrics. it just would not be impressive. eventually leakage would cause transistors to act like attenuators but that's ways off.

Certainly, you don't need HKMG but without it you cannot scale Tox by means of SiON using conventional poly (poly also suffers from depletion effects)... of course HKMG is performance oriented, it fixes the wall hit with SiON scaling a key performance knob (see Tinv in the equation above).

I am debating whether I want to push this discussion further ... perhaps after dinner, check back l8r. EDIT: See my responses above.

Jack

[WangChung]

So, we're fast approaching the picometer threshold. What then? Lithography with x-rays? Seems like we're approaching the end of the line in materials science when you're approaching the subatomic...

[kl0012]

A new leaks.
2C Llano 65W hmm...

http://news.ati-forum.de/index.php/n...-kommenden-apu

[Sn0wm@n]

humm zambezi 4 cores sounds nice

[zalbard]

Also 8 Cores @ 95W in Q2 11 - awesome!
Also there's a confirmation about AM3+ socket and it being compatible with AM3 chips.

[Mechanical Man]

Also 8 Cores @ 95W in Q2 11 - awesome!
Also there's a confirmation about AM3+ socket and it being compatible with AM3 chips.

But not vice versa. AM3+ Bulldozers are not compatible with AM3!

[Macadamia]

Why are there 3 Llano 2Cs- and 2 of them exact duplicates?

[slaveondope]

Why are there 3 Llano 2Cs- and 2 of them exact duplicates?

I'd imagine they have different gpu's.

[Oliverda]

Earlier I expected H2 for desktop Bulldozers. So this May date is a nice surprise for me.


(...and I can't wait to get a decent AM3+ mobo instead of this crappy asus.)

[FlanK3r]

ASUS DCrosshair V Extreme or maybe more than Extreme for me :P...whuuaaaaa, its look at April 2011 Zambezi launch. 8-cores, hexacores coming to me

[freeloader]

Looking forward to BD now. I was going to purchase a SB setup, but I think I'll wait the extra few months and see what BD delivers.

[Manicdan]

dosnt this go against JF saying BD is after Llano?

[saaya]

loveland? they seriously named a platform loveland?
who the h3ll is chosing those ridiculous names?

[Oliverda]

dosnt this go against JF saying BD is after Llano?

BD for servers will arrive after Llano.

[ubuntu83]

loveland? they seriously named a platform loveland?
who the h3ll is chosing those ridiculous names?

Don't know about who named it loveland but here is the link to the AMD CMO's blog ----> http://blogs.amd.com/nigel-dessau/ (ask him directly)

[generics_user]

dosnt this go against JF saying BD is after Llano?

Desktop BD was rescheduled from Q3 2011 to Q2 2011 and Llano from Q2 2011 to Q3 2011 on the last analyst day

[Manicdan]

BD for servers will arrive after Llano.

cool thanks

[JF-AMD]

Desktop BD was rescheduled from Q3 2011 to Q2 2011 and Llano from Q2 2011 to Q3 2011 on the last analyst day

I don't know if this is true. I don't think desktop BD moved at all. We had only said 2011 in public, never given any quarter granularity. So any "Q3 2011" date was probably based on speculation, not anything AMD said.

[Mechanical Man]

I don't know if this is true. I don't think desktop BD moved at all. We had only said 2011 in public, never given any quarter granularity. So any "Q3 2011" date was probably based on speculation, not anything AMD said.

So you think Llano delayed in favor to bring BD in more mass to market?

[Manicdan]

I don't know if this is true. I don't think desktop BD moved at all. We had only said 2011 in public, never given any quarter granularity. So any "Q3 2011" date was probably based on speculation, not anything AMD said.

the confusion, atleast on my part, was the constant BD after Llano, but my selective reading probably ignored the word "server" and thought all BD were going to be right around the same exact time.