AMD: 32nm issues fixed

[Chumbucket843]

At 22nm Intel will also use SOI and HKMG so AMD will be at a disadvantage.

that was a rumor based off of what an analyst said. most do no not agree with him either.

It'll be interesting silicon since it'll be 32nm SOI HKMG.

aside from the substrate there is very little Si at all actually. that's probably where the manufacturing troubles were coming from.

i wish that global foundries would actually publish something on their processes but i'm not expecting them to. until then their processes will remain fairly boring, at least from my perspective.

SSE5 was proposed ahead of intel. They decided for AVX, which was essentially a subset of SSE5.

In order to maintain binary compatibility we opted to join into the AVX instructions vs. forcing customers to have 2 different code sets.

The remaining SSE5 instructions are going to be implemented in Bulldozer in the form of FMA4 and XOP.

So, AVX + XOP + FMA4 essentially equals SSE5. So we are still delivering it, but doing it in a way that prevents a major fork in the codebase.

in no way is AVX a subset of SSE5. AVX is a much more radical departure from SSE.

i am not sure if you are familiar with assembly but hopefully you can see how different they are. notice how they arent even using the same registers.
http://developer.amd.com/cpu/SSE5/Pages/default.aspx
http://software.intel.com/en-us/arti...ons-intel-avx/

Architecure playing a huge role is exactly my point. Does AMD need SOI to help their product be competative?

Oh and ultraviolet is what we have been using for lithography for a very long time. Lithographic scanners use KrF excimer lasers of 248nm, and ArF of 193nm. I-line 365nm, from a mercury arc lamp, has been in use for much longer.

Maybe you mean EUV? Which is extreme UV. Problem is the cost of ownership for EUV is showing to be far too much.

Which is why immersion emerged. Immersion increases the NA, which increases the sigma, which increases the resolution.

And even with that it may take Intel up to 4 exposures for a single pattern, drastically increasing the cost of production.

We are going to need leap in lithography technology here soon.

i agree that we need a new approach to litho but increasing NA isnt entirely a good thing. depth of focus will become extremely shallow and requires very flat wafers. there are plenty of RET's but i dont see them keeping costs at a decent level.

maybe e-beam might provide better scaling. i dont know much about it but i already see huge issues with speed. with one or even several beams and billions of exponentially increasing etchings the beams must do will take a long time.