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Thread: Bulldozer Die Shot!

  1. #126
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    Last time i checked ivy bridge was suppose to have Q3-Q4 sampling and minor release in Mid-late Q4 2011. Now that could be because of the state of 32nm process back then idk but if BD does come before Q3 then most likely it will beat ivy bridge to the market. If it samples on Q1/Q2 it can be released by Q3.
    Coming Soon

  2. #127
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    So, there will be no high end SB products, the high end products will be IB ones?

  3. #128
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    Quote Originally Posted by Calmatory View Post
    So, there will be no high end SB products, the high end products will be IB ones?
    No. There is a 6-9 months timeframe from SB high end to IB high end products.

    From what it looks like, Intel decided to interleave the mainstream with high end and not release it in parralel. So you have SB mainstrean, 6 months later SB high end, 6 months later IB mainstream, 6 months later IB high end and so on.

    The high end products will be no different than Xeon DP equivalents, in fact they are the same product using the same socket. Basically, when Xeon products are ready, than will the high end also be launched. Xeon requiere more validation and since dies are larger, you need the process to be already ramped up ( that's mainstream task ).
    Quote Originally Posted by Heinz Guderian View Post
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  4. #129
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    I wonder if AMD will have serverparts as highend parts as well. That's how they've done with FX in the past. I guess we'll see highend and server bulldozer server first, around late Q2 with the rest to follow later, in Q3 or early Q4.

  5. #130
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    Quote Originally Posted by -Boris- View Post
    I wonder if AMD will have serverparts as highend parts as well. That's how they've done with FX in the past. I guess we'll see highend and server bulldozer server first, around late Q2 with the rest to follow later, in Q3 or early Q4.
    For that you would need boards with g34 or c32 socket, long time we saw server sockets for consumers from amd.

  6. #131
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    Here is my image for the die shot, I believe everyone was looking for 8 "cores" and 4 modules when it is actually only 2 modules and 4 "cores". Also used viethanhpro's sectioning of memory for L2/L3 cache's. I believe it is a photoshopped 4 module down to 2, as well as some of the internal bits also being moved around in addition to blurred and scaled.

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  7. #132
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    I think you are wrong .It's 8core/4module die alright,but deliberately altered.

  8. #133
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    fail. there is no separate memory space for different data types in x86. the L2&3 can hold instructions and data.

    there is no point in trying to get any information out of that die shot. they clearly knew what to screw with because it is very confusing.

  9. #134
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    It is an 8-core as I have said before. But, as I have also said before, don't do the math on that one, you will only be wrong.
    While I work for AMD, my posts are my own opinions.

    http://blogs.amd.com/work/author/jfruehe/

  10. #135
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    Quote Originally Posted by JF-AMD View Post
    It is an 8-core as I have said before. But, as I have also said before, don't do the math on that one, you will only be wrong.
    let them do some math it's funny

  11. #136
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    Quote Originally Posted by JF-AMD View Post
    It is an 8-core as I have said before. But, as I have also said before, don't do the math on that one, you will only be wrong.
    I count eight cores in four modules with shared L2 cache. How's my math so far?

  12. #137
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    Quote Originally Posted by marten_larsson View Post
    I count eight cores in four modules with shared L2 cache. How's my math so far?
    L2 is shared on module level,if that's what you meant.L3 is shared between all the modules(a victim cache for L2s).

  13. #138
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    Quote Originally Posted by Stukov View Post
    Here is my image for the die shot, I believe everyone was looking for 8 "cores" and 4 modules when it is actually only 2 modules and 4 "cores". Also used viethanhpro's sectioning of memory for L2/L3 cache's. I believe it is a photoshopped 4 module down to 2, as well as some of the internal bits also being moved around in addition to blurred and scaled.

    That is not how you build a processor, the FPU is a part of each core, it isn't something you put on other side of the die. Besides, the two interger parts of each module is different in your version, they shouldn't be.
    So, each big rectangle in the corners of the die is a module. Including two integer parts and FPU units. if you look at the module in the bottom right corner you can clearly see some small parts of it is mirrored, that is the cores. The parts that isn't mirrored is some cache, decode and other parts that is shared.
    And as others already pointed out, you don't have different caches for different data types.

  14. #139
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    Quote Originally Posted by informal View Post
    L2 is shared on module level,if that's what you meant.L3 is shared between all the modules(a victim cache for L2s).
    Of course. Do you think I'm blind or something?!

    On a side note: I'm eagerly waiting for Bulldozer to launch. Looking at how Ontario seems to be performing I believe AMD will be in a good position to gain some market share when Ontario, Llano and Bulldozer have launched (Ontario and Bulldozer being most impressive). Although, I will miss the Formula 1 inspired code names.

  15. #140
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    From the looks of it, do you guys think BD will outperform Core i7's?

  16. #141
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    Quote Originally Posted by HelixPC View Post
    From the looks of it, do you guys think BD will outperform Core i7's?
    We don't know,we don't have much information at the moment. But from the looks of it,since you asked,yes I think that this will be the case.The cores are improved,targeted clocks are supposedly higher than with Deneb/Thuban(deeper pipeline,L1 cache changes),number of cores went up(33%),new FPU,complete ISA support,new power gated Turbo etc. All tells a very promising story,but until it launches we can only speculate.

  17. #142
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    Quote Originally Posted by informal View Post
    We don't know,we don't have much information at the moment. But from the looks of it,since you asked,yes I think that this will be the case.The cores are improved,targeted clocks are supposedly higher than with Deneb/Thuban(deeper pipeline,L1 cache changes),number of cores went up(33%),new FPU,complete ISA support,new power gated Turbo etc. All tells a very promising story,but until it launches we can only speculate.
    that sounds a lot like fermi.

    seriously, we know the architecture is good. the question to be asked is how well glofo can make their 32nm process from a perspective of time, performance, yields and capacity. is bulldozer focused on design for manufacturing? is it focused on design for yield? with all of the talk of modularity validation and verification should be fast but what if the upper metal layers have cracks or severe fringingor high variablity, resulting in much lower frequencies from skewed clock distribution? personally i wont describe bulldozer in any terms of performance before launch, including ipc.

  18. #143
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    I think AMD went for DFM with Shanghai/Deneb(and will continue to do so in future). The GloFo slides show better than expected clock targets(N+2) but yields are not where they want them(yet).

  19. #144
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    Quote Originally Posted by informal View Post
    I think AMD went for DFM with Shanghai/Deneb(and will continue to do so in future). The GloFo slides show better than expected clock targets(N+2) but yields are not where they want them(yet).
    Maybe to an amateur. To professionals, that is a process out of control.

    Quote Originally Posted by Paul Demone
    32nm HKMG / Fmax distribution ?

    They seem to be suggesting that they're doing better than the previously expected median of whatever that is...

    max frequency of something or other?
    That is max frequency.

    It is one of those things that will impress the more technically
    inclined AMD supporters who will inform the mouth breathers
    and all will cheer and rejoice. It takes an experienced industry
    type to read the real message there.

    So fmax yield skewing high like that is good right?

    Well fmax doesn't happen in isolation. It is highly correlated
    to leakage and electric field strength related reliability and
    aging effects. You get a lot of fast parts but those parts run
    very hot, have high sleep mode power, and high failure rates
    in the flat part of the bathtub curve.

    That graph is not of a process 1) in control, or 2) meeting its
    desired target by a long shot. You *want* a nice tight bell
    curve approximately centered around your target median.
    Quote Originally Posted by Heinz Guderian View Post
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  20. #145
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    Quote Originally Posted by savantu View Post
    Maybe to an amateur. To professionals, that is a process out of control.
    Great.. Paul D. talking to terrace215 on an investor board.
    Highly regarded professionalism in relentlessly spamming FUD.

    http://investorshub.advfn.com/boards...ge_id=53966494


    Regards, Hans

  21. #146
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    Quote Originally Posted by savantu View Post
    Maybe to an amateur. To professionals, that is a process out of control.
    And you would be a professional right?

    Well, professionalism means being impartial and not judging with your "love".

    From your posts i don't see that, your always looking at the bad side of the things instead of looking at both sides of the story and just appreciating what the guys at AMD are working on.

  22. #147
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    Quote Originally Posted by Hans de Vries View Post
    Great.. Paul D. talking to terrace215 on an investor board.
    Highly regarded professionalism in relentlessly spamming FUD.

    http://investorshub.advfn.com/boards...ge_id=53966494


    Regards, Hans
    Nice to know you read Intel's invest boards. Btw, your reply also speaks volumes about your professionalism since you attack the speaker and not his arguments.

    You claim you have experience in IC design. Do you agree or disagree with Paul's assesement, irrespective of where his preferences lie ? You can also decline if you believe your cannot make this judgement based on your experience. Let's keep the signal up and noise down. Stick to the facts.


    Quote Originally Posted by Florinmocanu View Post
    And you would be a professional right?

    Well, professionalism means being impartial and not judging with your "love".

    From your posts i don't see that, your always looking at the bad side of the things instead of looking at both sides of the story and just appreciating what the guys at AMD are working on.
    Let's get the fact straight. AMD 32nm products are delayed because GF has problems with the 32nm process. ( hardly unexpected given their SOI+gate 1st aproach )
    Informal posts a comment about slide 17 from the GF presentation regarding Freq distribution of the parts and considers it evidence of a good process since most parts hit N+2 frequency. ( N being the expected median ).
    At first I believed that too, as amateur I thought : " What's the fuss with GF 32nm since it yields above target bins ? " Then I saw a post by Paul who has 30 years experience in IC, both analog and digital, holds several patents for memories,etc and he explained clearly things aren't right.
    Distribution should follow a gaussian pattern with a bell centered around the median.
    And then you and Hans come and snide about everything but the actual argument. Target the argument and not the messenger rings a bell ?
    Quote Originally Posted by Heinz Guderian View Post
    There are no desperate situations, there are only desperate people.

  23. #148
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    Quote Originally Posted by savantu View Post
    Nice to know you read Intel's invest boards. Btw, your reply also speaks volumes about your professionalism since you attack the speaker and not his arguments.

    You claim you have experience in IC design. Do you agree or disagree with Paul's assesement, irrespective of where his preferences lie ? You can also decline if you believe your cannot make this judgement based on your experience. Let's keep the signal up and noise down. Stick to the facts.




    Let's get the fact straight. AMD 32nm products are delayed because GF has problems with the 32nm process. ( hardly unexpected given their SOI+gate 1st aproach )
    Informal posts a comment about slide 17 from the GF presentation regarding Freq distribution of the parts and considers it evidence of a good process since most parts hit N+2 frequency. ( N being the expected median ).
    At first I believed that too, as amateur I thought : " What's the fuss with GF 32nm since it yields above target bins ? " Then I saw a post by Paul who has 30 years experience in IC, both analog and digital, holds several patents for memories,etc and he explained clearly things aren't right.
    Distribution should follow a gaussian pattern with a bell centered around the median.
    And then you and Hans come and snide about everything but the actual argument. Target the argument and not the messenger rings a bell ?


    All is not well with Intels 32nm process either and Intel has much more experience with 32nm than GF. Now the problem with Intel's 32nm gives rise to lower production and another thermal related problem "Cant go much further into either"

    Anyways Intel is working its arse off to fix the problems and quite soon enough these will be rectified, i know that the thermal problem will be fixed before sandy bridge goes into full out production.

    Well the fact of the matter is both GF and Intel has problems with 32nm, maybe GF has SOI+gate 1st approach to thank but that does not dim the fact that "32nm is harder to adopt than 45nm"
    Coming Soon

  24. #149
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    Yields is always bad in the beginning of each processes, no news there. How can you possibly try to use this fact against AMD and GloFo?
    Was Intel in equally deep when their 32nm yields was bad? Is every company doomed every time they change a process?

    EDIT: I don't think anyone would expect GloFos 32nm to be a mature process yet. That the yields isn't there they want them is what we expect at this point.
    Last edited by -Boris-; 09-06-2010 at 11:27 PM.

  25. #150
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    Nah, you got it wrong Savantu. The problem is not that you comment quite critically over some things going on at AMD/GF.

    The problem is that we don't see you doing the same on Intel matters/threads. If you would be impartial and as hard on Intel as you are on AMD than nobody would care what your attitude is.

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