AMD Ontario APU pictured,die size ~77mm^2

[richierich]

Time to upgrade my Dell 11z with SU4100 processor as soon as one of these hits the market. Currently can't play any 3D demanding games (Company of Heroes or steam games).

[Calmatory]

How... Intels superiority is beaten by.. TSMC!? Despite 45 vs 40mm.. 100 % more transistors < 90 % of the size, and with computer aided layout.. What?

I ain't buying :O

[Raqia]

Is Ontario / Zacate supposed to be dual core? I guess the slide does say "cores."

[Chumbucket843]

How... Intels superiority is beaten by.. TSMC!? Despite 45 vs 40mm.. 100 % more transistors < 90 % of the size, and with computer aided layout.. What?

I ain't buying :O

it's this thing called low power. it is a much higher priority for TSMC.

then we have ATi's advantage in graphics and intel's quite unimpressive atom uarch.

[bamtan2]

http://www.chip-architect.com/news/ontario_vs_atom.jpg
Regards, Hans

these pictures exactly describe what nvidia chief scientist bill dally says. few very fast cpu cores with many gpu cores. that is the chip of the future.

http://www.xbitlabs.com/news/cpu/dis...of_Nvidia.html

"I don't see convergence between latency-optimized cores and throughput optimized cores. The techniques used to optimize for latency and throughput are very different and in conflict. We will ultimately have a single chip with many (thousands) of throughput cores and a few latency-optimized cores so we can handle both types of code,"

[Sn0wm@n]

that looks like cache to me. the four quadrants in the middle is most likely where the bobcat and gpu cores are.

i guarantee you they wont make a 40sp igp. that's not possible with their arch.

huh??? so you expect how many sp ????

[spursindonesia]

i wish the worst for every company because i am a consumer. i want the worst margins possible. there is no sense in supporting a corporation that doesnt care about my community. all amd wants is my money and they will have to earn it. they certainly are not entitled to it for being amd although for some this isnt a problem.

I wish them the best not for their interest, a melancholy nonsense, but for my own interest, since bad AMD products mean near monopoly behaviour from Intel in the middle and upper segments of the market and less R&D money for AMD for future technological advancement.

[mAJORD]

Well If it's as good in person as it is on paper


.

[Chumbucket843]

huh??? so you expect how many sp ????

a SIMD in ATi's architecture is a 16 wide vector with 5 VLIW units each. 16*5=80

there are 4 SIMDs in rv670/r600, 10 for rv770, and 20 for cypress.

my area estimate for a single SIMD core including tmu's is ~16mm2 and the area of the gpu core in bobcat is ~30mm2. 160sp or 80sp is what i would be guessing, preferably 160.

it will be interesting to see if they go for 80sp but go for 8 tmu's and 4 rops. i think that will be more likely.

[STEvil]

now all we need are netbooks/etc with external PCI-E 16x access so you can plug in an external GPU at full performance.

[Sn0wm@n]

Well If it's as good in person as it is on paper


.

epic pic man

a SIMD in ATi's architecture is a 16 wide vector with 5 VLIW units each. 16*5=80

there are 4 SIMDs in rv670/r600, 10 for rv770, and 20 for cypress.

my area estimate for a single SIMD core including tmu's is ~16mm2 and the area of the gpu core in bobcat is ~30mm2. 160sp or 80sp is what i would be guessing, preferably 160.

it will be interesting to see if they go for 80sp but go for 8 tmu's and 4 rops. i think that will be more likely.

that would be epic ...

[ajaidev]

[]http://www.chip-architect.com/news/ontario_vs_atom.jpg[/IMG]

Regards, Hans

Thanks Hans, this means that a properly clocked "650mhz and up" gpu has the potential to come near the performance of the sandy bridge part that was tested by anandtech.

Just think a low end part such as this challenging a Intel behemoth in lower end games where the added cpu power cant do much. I love where the fusion is headed. The lack of a L3 also suggests that this is wired similarly as a llano.

EDIT: I wonder if GPU turbo is a part of the feature set?

[spursindonesia]

This chip 80 SPs GPU will toy with Sandybridge 6 EU core GPU in graphic task, but perhaps still short of challenging the 12 EU core one. If its CPU performance is really quite close with AMD old K8 dual core, then low res. low detail/complexity gaming won't be bottlenecked that bad by the CPU part of the core.

[cal_guy]

This chip 80 SPs GPU will toy with Sandybridge 6 EU core GPU in graphic task, but perhaps still short of challenging the 12 EU core one. If its CPU performance is really quite close with AMD old K8 dual core, then low res. low detail/complexity gaming won't be bottlenecked that bad by the CPU part of the core.

The anandtech article now states that the Sandybridge preview probably used a 12 EU core.

http://www.anandtech.com/show/3876/i...bridge-part-ii

[saaya]

it's this thing called low power. it is a much higher priority for TSMC.

then we have ATi's advantage in graphics and intel's quite unimpressive atom uarch.

unimpressive? how is that possible? it was designed by the same guys that came up with prescott and tejas... which was later cancelled... twice... ^^

[kl0012]

http://www.chip-architect.com/news/ontario_vs_atom.jpg

To me it looks like cache, not cpu core.

Regards, Hans

To me it looks like a cache area (fairly regular structure).

SRAM cell size for intel's 45nm process: .346um^2
high density SRAM cell size for TSMC's 40G process: .242um^2

There are different SRAM cells for different purposes (high density/low speed, high current/high speed, single ported, dual ported e.t.c). Not sure if you compared the same.

[superrugal]

[IMG]http://www.chip-architect.com/news/ontario_vs_atom.jpg[IMG]

Regards, Hans

Hi Hans, are those truly two "bobcat core" not "bobcat cache"? To me it's unbelievable that the two part upon the die are CPU cores.

[Lightman]

To me it looks like a cache area (fairly regular structure).


There are different SRAM cells for different purposes (high density/low speed, high current/high speed, single ported, dual ported e.t.c). Not sure if you compared the same.

Yes, but remember that Bobcat is using half-speed L2 cache which means they can go for highest densities

[Oliverda]

RS780 (55nm) die size is 64mm² and it has 40 shaders plus HT link and PCI-E controllers.

[kl0012]

Yes, but remember that Bobcat is using half-speed L2 cache which means they can go for highest densities

Now I wonder... As I remember P-3 Coppermine was up to 30% faster the Katmai having only half cache size of Katmai (but at full speed). And Tualatin (512Kb) has increased the perf. by another 10-20%...

[cal_guy]

a SIMD in ATi's architecture is a 16 wide vector with 5 VLIW units each. 16*5=80

there are 4 SIMDs in rv670/r600, 10 for rv770, and 20 for cypress.

my area estimate for a single SIMD core including tmu's is ~16mm2 and the area of the gpu core in bobcat is ~30mm2. 160sp or 80sp is what i would be guessing, preferably 160.

it will be interesting to see if they go for 80sp but go for 8 tmu's and 4 rops. i think that will be more likely.

ATI also supports 8 way SIMD. RV610, RV620, RV630, RV635, RV710, RV730, and Cedar are all examples of ATI gpu in 8 way format. Also all current AMD IGP are 40 SP versions.

[Kej]

a SIMD in ATi's architecture is a 16 wide vector with 5 VLIW units each. 16*5=80

there are 4 SIMDs in rv670/r600, 10 for rv770, and 20 for cypress.

my area estimate for a single SIMD core including tmu's is ~16mm2 and the area of the gpu core in bobcat is ~30mm2. 160sp or 80sp is what i would be guessing, preferably 160.

it will be interesting to see if they go for 80sp but go for 8 tmu's and 4 rops. i think that will be more likely.

16 SPU's is not a fixed value for ATI's SIMD engine, they can make it 8
or 32 if they so like.

With todays architecture ATI have a quad TMU with each SIMD engine.
If you look at shader vs TMU ratio you can see that many low end
Radeon's are 8 wide, 40SP's, for example.

[ajaidev]

Forgot to add you can clearly see a line across the core "almost in the middle" and the same is present on the floor plan, now if you look at L2 you again can see the line whos first block is created smaller than the second one same as in the floor plan.

[informal]

Now I wonder... As I remember P-3 Coppermine was up to 30% faster the Katmai having only half cache size of Katmai (but at full speed). And Tualatin (512Kb) has increased the perf. by another 10-20%...

And with this half clock L2 Bobcat is supposed to be on par with Core based Pentium's we have today.

[Opteron146]

http://www.chip-architect.com/news/ontario_vs_atom.jpg

Regards, Hans

Thanks for the comparision.

Just one information, Pineview's GPU ist not PowerVR based, it is an GMA3150, just the usual Intel stuff ..
Mentioned e.g. here:
http://www.anandtech.com/show/2889

A PowerVR core was only used in the GMA500, if u google it, youÄll find lots of Linux discussions, because it was not supported by the intel drivers, due to the PowerVr core

E.g:
http://www.linuxjournal.com/content/...-and-community