yes i couldnt agree more, there are some issues with sharing of the bus, and the thing about the packet optimizations, is that if you go too far you will end up adding latency, so there is a definite inherent weakness of the interface. not neccesarily the lanes themselves, but that they terminate at the IOH, which in turn handles traffic. some of the serious advances with sandy bridge should be absolutely phenomenal, such as the inclusion of the pic-e controller onto the chip, should handle the throughput much faster, not to mention pci-e 3.0. the pci-e 3.0 controllres are where my next goal lies. 600,000 iops and a dual 1.4 ghz ROC on the next gen of the LSI. hopefully areca is going to implement this same controller into their line of products. i think now that they are over the whole marvell fiasco you should see much faster r&d in the future, which is an impression i have gotten from speaking with them.
the nand module you are speaking of is an excellent concept, and i am sure that one day we will see some implementation of that, as a matter of fact things are headed that way with memresistor (am i saying that right?) which could double as storage and ram at the same time, exciting stuff! i could be wrong, but i believe that the implementation you are speaking of is actually only using the power form the memory socket to power the device, yet it has a sata port on the side, and that is why they arent too excited about it, it still connects via the sata port i think. future versions will go over the memory lanes themselves. they do seem like very good ideas though. its crazy that a year ago everyone was thinking that getting the nand on the pcie was the way to go...but things are advancing so fast, now they are shifting to memory/ram implementations over the ram slots!
my testing continues today, only have made about three solid runs, having issues with my system...
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