Right now the cores consist of 800/5(4+1) SIMD processors(160). With the 4+1 -> rumour the cores would consist of 800/4 SIMD processors(200). That's a 25 % increase while the SP count remains the same.
The catch here is that with 4+1 configuration there is one SP more or less unused most of the time, 4 SP configuration eliminates this and allows denser packing of the SIMD processors. So they can add more SIMD processors and thus bring the SP count to 800 while working with same die area limitation.
I am very doubtful towards this 4+1->4 theory though, I'd take it as 4+1 -> 3+1. Well, still effectively cutting number of ALUs per SIMD processor from 5 to 4. But the main idea is that there's hardly ever such cases that the instruction level parallelism would be so high that all the ALUs would be busy, so cutting one off isn't a big deal and only gets costy in very rare cases.




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