AMD's Bobcat and Bulldozer

[Hans de Vries]

http://www.xbitlabs.com/articles/cpu...0_6.html#sect0

page 251 of: http://support.amd.com/us/Processor_TechDocs/25112.PDF

A.3 Superscalar Processor

The AMD Athlon 64 and AMD Opteron processors are aggressive, out-of-order, three-way
superscalar AMD64 processors. They can fetch, decode, and issue up to three AMD64 instructions
per cycle with a centralized instruction control unit (ICU) and two independent instruction
schedulers—an integer scheduler and a floating-point scheduler. These two schedulers can
simultaneously issue up to nine micro-ops to the three general-purpose integer execution units
(ALUs), three address-generation units (AGUs), and three floating-point execution units. The
processors move integer instructions down the integer execution pipeline, which consists of the
integer scheduler and the ALUs, as shown in Figure 6 on page 252. Floating-point instructions are
handled by the floating-point execution pipeline, which consists of the floating-point scheduler and
the floating-point execution units.

or alternatively:

http://www.chip-architect.com/news/2...Core.html#1.20


But don't forget that the average number of ALU instructions is something like 0.4/cycle
which is 4, 5 times less as two ALUs can provide.


Regards, Hans