Here is what it means.
Bulldozer cores are like Intel Hyper-threading cores.
The primary difference is that AMD throws more transistors at the problem by giving each thread it's own set of integer execution units. Added to the fact that AMD’s distributed schedulers and instruction grouping. This is a clear architectural trade-off of performance and decreased control complexity versus size and increased execution complexity. Replicating two full featured ALUs uses more die area, but provides higher performance for certain corner cases, and enables a simpler design for the ROB and schedulers.
The honest truth is if NO CPU designed yet, can keep a constant throughput of 2 instructions per clock. So the more efficient design of the Integer cores, suggest that we shouldn't expect any performance drop at all. [For 99.9% of all user applications ]




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