Quote Originally Posted by kl0012 View Post
You're probably right saing that ALUs in K10 were underutilized but I have a hard time to belive that the average IPC was less then 2. Now AMD is adding many stuff to improve ALU utilization but in the same time is reducing number of ALUs. Where is the logic?
They are optimizing for server application throughput, at the expense of client low-threaded performance. That might make sense for them, considering the initial target market is virtually all server/hpc. In client, they have Llano in the middle, and Ontario down low... so maybe they decided they couldn't be all things to all segments with BD.