Yeah the buswidth and the ROP seems quite puzzling to me up to this moment. I think if ATi push for 384 bit for Cayman & 256 bit for Bart, they won't be pad limited, but the die size might grow excessively since 384 bit means 48 ROP & 256 bit 32 ROP consecutively. But with the slowing of GDDR speed increasing pace & the added die size from core improvement using the same process node, it's quite reasonable for them using the larger buswidth & the associated added ROP, if the chip performance justifies that. OTOH, that would mean the end of sweetspot strategy, or not ?
aarrggh, i should stop speculating by now, a layman shouldn't think too much out of his league.
Originally Posted by spursindonesia
Yeah the buswidth and the ROP seems quite puzzling to me up to this moment. I think if ATi push for 384 bit for Cayman & 256 bit for Bart, they won't be pad limited, but the die size might grow excessively since 384 bit means 48 ROP & 256 bit 32 ROP consecutively. But with the slowing of GDDR speed increasing pace & the added die size from core improvement using the same process node, it's quite reasonable for them using the larger buswidth & the associated added ROP, if the chip performance justifies that. OTOH, that would mean the end of sweetspot strategy, or not ?
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