JEDEC reveals DDR4 roadmaps and specs

[Particle]

nobody is saying we should stop ddr4 research
once we need it, it will be ready, im sure... actually its much more likely that itll be ready BEFORE we need it

what im saying is that:
1.) itll be quite a while before it comes out
2.) i wouldnt expect any notable performance boosts from ddr4 once it does...

Looks like we're on the same page then.

why has memory become a minor perf boost? back in DDR1 days it was pretty noticeable, have new instructions relied more on cache than memory chips?

I'd say the boost was more significant due to these three pressures:
- Caches on CPUs were smaller and slower leading to the core being starved more often

- The memory technologies were much slower than what we have today. It's easy to be wowed by gains at the low end of a technology like with CPUs in the Pentium/Pentium II days because it's a lot easier to notice. Remember being impressed by CPU upgrades back then in terms of how much faster a system felt? That just doesn't really happen anymore since the CPUs of yesteryear are already so fast for general purpose activities. Same concept.

- The gains were larger, too, due to a switch from SDR to DDR signaling. That alone gets you a virtually free doubling of throughput at the same frequency without sacrificing latency. We don't get to do that again since we're already using it. We can add more phases of clock cycles, but QDR is about the practical limit.

[nn_step]

interesting graphs...
but they are more of a general overview i think... they dont look very accurate, then again i dont think they were ever meant to be very accurate


this is already possible with ddr3 afaik...

true... diont you think theres some room for improvement through caching branching and prefetching though? still thats going to happen either in the imc or memory switch chip...

caching is already being done [Performance significantly limited by Cache sizes and working set]

pre-fetching is already being done [AMD and Intel perform this extensive where possible]

Not to mention those two technologies are not new and have been implemented in systems since 1972.

The only improvements left in memory are bandwidth based. Unless of course new revolutionary memory types are used [or using Z-RAM with its 3ns claimed response times]

Which is alright if we don't expect single thread performance to continue to climb much. Since multi-core systems are bandwidth hungry and more tolerant of weaker latencies.

[Sn0wm@n]

QDR or even HDR ... they wont ever stop and i dont ever want them to stop ... faster silicon always travels down to other area of social activities .... + its also cheaper in the end that way with the current tech cycle of life ....

[Particle]

I'm not sure it'll go much beyond QDR. It's theoretically possible of course, but timing is a major issue as you add clock phases. It would probably be better just to increase clock frequency, and that's generally what we've seen in the past with DDR2 and later DDR3. The DDR interface just takes advantage of what is essentially a free improvement by transmitting on both the rising and falling edge instead of just one or the other like had traditionally been the case. Generally speaking, in digital logic, reads are done on one edge and writes on the other. To get QDR you have to get another clock signal of identical frequency perfectly in sync with the first and out of phase by 90 degrees. If you want to go 6DR you'd need three that are 60 and 120 degrees, for 8DR you're looking at 45, 90, and 135. And so on. It gets REALLY hard to do compared to increasing frequency. Again, it's theoretically possible, but it's not the low hanging fruit that DDR is.

I've had some experience in this area with some digital logic design work as I've designed and used memory controllers before. I'm not a professional R&D team or anything, but I am at least more familiar than a random person on the street.

[Unoid]

Looks like DDR4 will finally allow onboard/die GPU's like amd's upcoming fusion/llano to have the bandwidth they need, especially if the rumors of quad channel controllers are true.

[hollo]

lga1366 uses triple channel, beckton uses quad-channel, magny cours uses dual dual-channel, so someone needs it

[570091D]

why has memory become a minor perf boost? back in DDR1 days it was pretty noticeable, have new instructions relied more on cache than memory chips?

it seems to me that the biggest bottle neck in computers today is the HDD. it's great to see advances in memory, but i'm not going to rush out and spend $650 on a new memory set again (thinking back to the release of DDR3-2000).

lga1366 uses triple channel, beckton uses quad-channel, magny cours uses dual dual-channel, so someone needs it

indeed, servers need the bandwidth.

[Hornet331]

The only improvements left in memory are bandwidth based. Unless of course new revolutionary memory types are used [or using Z-RAM with its 3ns claimed response times]

Pfff z-ram.. an ongoing fairy tale... for how long do we here that it will replace sram, dram etc., especial form amd, half a decade?

But fear not T-ram for the rescue...

[nn_step]

Pfff z-ram.. an ongoing fairy tale... for how long do we here that it will replace sram, especial form amd, half a decade?

But fear not T-ram for the rescue...

Since 1/19/2006 to be precise.

However this is not surprising given the typical time between invention and market.

[Mungri]

And the first batches of DDR4 will cost £300 for 4 Gb of standard Jedec spec versions.

If its anything how DDR3 was.

[Particle]

Pfff z-ram.. an ongoing fairy tale... for how long do we here that it will replace sram, dram etc., especial form amd, half a decade?

But fear not T-ram for the rescue...

AMD bought the rights to it and said they'd investigate using it in the future, but the tale that its introduction is immanent is nothing but the fabrication of computer users gossiping, as far as I know.

[saaya]

why has memory become a minor perf boost? back in DDR1 days it was pretty noticeable, have new instructions relied more on cache than memory chips?

ddr1 cut actual latency almost in half, thats why afaik... qdr would be the next step but it was more complex and expensive to implement... with chips its all about being cheap... the cheapest "good enough" tech usually prevails...

the biggest jump in memory performance in my experience was sdr to ddr, and it was accompanied by the fsb going ddr as well, which was probably a notable part of the boost as well. after that the second biggest boost was going ddr single channel to dual channel... everything after that was only measurable in benchmarks for me...

about more bandwidth making sense for more cores, yeah... now we only have to find a way to actually USE those cores
i think single thread performance will continue to improve, i hope so at least... its going to be at least a decade until single thread performance wont really matter anymore...
lets hope caches grow big enough to provide memory boosts by slowly replacing dram, at least for single thread scenarios...

[Mungri]

Yea, in video games there is absolutely minor gain to be had from going from Dual Channel 800 Mhz DDR2 > Triple Channel 2133 Mhz DDR3.

Which is really annoying, considering the speed and bandwidth difference between the two.