Quote Originally Posted by savantu View Post
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IPC and frequency are conflicting aproaches. You can't have both, it's one or the other. Your theoretical Bulldozer is like having a Pentium 4 with the IPC of Core 2. Pigs will learn to fly sooner than you will get such a CPU.
That's not what I said. I said, lower IPC than Phenom II while clocking higher and Phenom II has a lower IPC than Core 2 AFAIK.
Quote Originally Posted by savantu View Post
To get a lot of IPC you need very wide cores with lots of execution units, complex decoders able to extract the parallelism out of the instruction stream and lots of buffers to keep a mountain of data in flight through the chip. All that limits the frequency you can get. In other words, if your goal is IPC, you give up on frequency. Complex circuits clock badly and burn a lot of power.
You could also go for a more hybrid approach, like double clocking those parts in a core that make sense. Clock domains within a single core in other words. You could for example run the schedulers and execution units at double the clockspeed of the fetch and decode stage. I'm not saying they will, but it's another approach.

As I just said, we know very little about Bulldozer and there is a very slight chance that AMD may really surprise us. I'm just being cautiously optimistic.