Quote Originally Posted by saaya View Post
hmmm... correct me if im wrong, but isnt every modern x86 cpu blocks of risc logic with an x86 decoder on top? so then the decoder needs to be able to spit out code that a gpu core can process, and the latter has to be able to spit out data in a way it can be built into an x86 compatible result again... its basically adding a new type of fpu block to the cpu... so the gpu core wouldnt have to execute x86 code, right?
please excuse my lack of knowledge about this
im not enitirely sure how cpu's break down instructions. it probably takes a simple instruction and breaks it down into simpler operations. you concept of digital logic is not right. an ISA is just a bunch of instructions a processor executes. the processor doesnt need special logic for that particular isa. it just needs to be able to execute every instruction.

here is a simple decoder. its like a switch in a network. its not some complex decrypting magic.
http://www.asic-world.com/digital/co...er_using_Demux

i understand what you are saying: could an x86 decoder allow instructions to run on a gpu? no. there are many issues. gpu's are still asic's. they are designed around directx. they dont support all of the features that would be needed in a cpu and they are very different architecturally. for instance sse has 8 GPR's(general purpose registers). evergreen has 128GPR's. both are 128 bits wide. an sse programmer cant use 128 gpr's because 120 of them dont exist!