Basically, your statements are that AMD didn't just take a current Deneb K10 Core and inserted in on a Llano, but that it suffered modest modifications to the K10 Core design. I don't know anything about how to recognize the transistors blocks (With the exeption of usually the obvious Cache L2 and L3), but if they were added on a revision of the K10 Core in Llano, then it is interesing. Not counting AVX because they requiere applications capable to use it, how do you think that the new Integer unit and double TLB could impact performance?