Dresdenboys' blog: AMD Bulldozer - Patent based research

[Dresdenboy]

Well if this is in fact true and single core/thread perf. of BD could be the same or possibly lower than MC, isn't this really dangerous for Desktop performance on these chips considering single thread perf. is quite important there?

How is BD supposed to compete with Intel's future gen. architecture with single threaded perf. lower than MC? I mostly doubt this will be true but hearing Dresdenboy comment on this possibility worries me.

This was just an argument against the per core performance analysis. What counts is how fast your apps run with what energy consumption and at which price. Also matters become more complex because of more advanced energy management methods etc. Recently I tried to scale back the Interlagos performance advantage to 4 and 6 cores (2 and 3 modules respectively) and got performance numbers comparable to 4.8 and 3.8 GHz quad- and six-core K10. OTOH I also already heard, that BD scales really well. This would mean somewhat lower numbers for the smaller core counts.

And then add an even more efficient turbo for the lowly threaded apps or even such ones, which don't utilize some of the units that much (e.g. FPU, caches).. We might see scalable caches, TLBs, FPUs, maybe even integer cores... A lot of such stuff has been patented. So I don't have problems to agree with informal here.

BTW I'll be offline for a week. So don't expect updates or answers during that time, except I find some internet terminal

[-Boris-]

I don't get it.
What makes dresdenboy and everyone else believe that the 4 pipelines should be translated to 2 ALUs and 2 AGUs?
In Athlon the 3 pipelines consists of 3 ALUs and 3 AGUs.

What I read as 33% more integer performance, others read as 33% less.
Explain please.

[vietthanhpro]

I don't get it.
What makes dresdenboy and everyone else believe that the 4 pipelines should be translated to 2 ALUs and 2 AGUs?
In Athlon the 3 pipelines consists of 3 ALUs and 3 AGUs.

What I read as 33% more integer performance, others read as 33% less.
Explain please.

1 pipeline has ALU +AGU, not ALU or AGU.

[-Boris-]

1 pipeline has ALU +AGU, not ALU or AGU.

Exactly!
I simply don't understand why everyone believes in dresdenboys 2 pipeline config for Bulldozer.

[vietthanhpro]

Exactly!
I simply don't understand why everyone believes in dresdenboys 2 pipeline config for Bulldozer.

AMD don't confirm !
i think 3 pipelines for ALU+AGU, 1 pipeline for load/store unit.

[Dresdenboy]

Please calm down. These numbers are just multiple hypothesis. One is based on stuff like this:

Within each cluster 150 , execution units 154 may support the concurrent execution of various different types of operations. For example, in one embodiment execution units 154 may support two concurrent load/store address generation (AGU) operations and two concurrent arithmetic/logic (ALU) operations, for a total of four concurrent integer operations per cluster.

(contained in several Bulldozer related patents)

Some of my related posts:
2 ALU/2 AGU hyptothesis:
http://citavia.blog.de/2009/11/13/ho...-have-7366681/
4 ALU/4 AGU hypothesis:
http://citavia.blog.de/2009/11/16/bu...ought-7383623/
2 ALU/2 AGU hyptothesis by Hiroshige Goto:
http://citavia.blog.de/2009/12/19/bu...ussed-7605288/
2 ALU/2 AGU possible confirmation reported by Yusuke Ohara:
http://citavia.blog.de/2010/01/11/an...japan-7737558/

But it could also go into another direction:

In one embodiment, the ALU 220 and the AGU 222 are implemented as the same unit.

(also from some patents related to a BD like architecture, maybe a successor)

And to round it up there is my hypothesis, that there are just 2 ALUs and 2 AGUs, but running at a significantly higher clock than today (maybe even as a double pumped design).

What counts, is the resulting performance of the chip and not, if it has 4 ALUs/4 AGUs at only 2GHz. The goal is not to achieve the ultimate absolute raw power per clock, but the highest performance for different workloads inside a given TDP or ACP "envelope".

[-Boris-]

And to round it up there is my hypothesis, that there are just 2 ALUs and 2 AGUs, but running at a significantly higher clock than today (maybe even as a double pumped design).

What counts, is the resulting performance of the chip and not, if it has 4 ALUs/4 AGUs at only 2GHz. The goal is not to achieve the ultimate absolute raw power per clock, but the highest performance for different workloads inside a given TDP or ACP "envelope".

So you say two pipelines despite AMDs charts saying otherwise, and assume a higher frequency, maybe doublepumped pipes to compensate?

EDIT:
Still don't get it. Your theory about 2 Pipes seems to be based on charts of performance hinting similar performance per thread. But when you get information about higher integer performance you start talking about higher frequencies instead of the four pipes.

That performance chart could be based on a 4 module 8 core interalgos, we still don't know if the 16 core part will be 2011 or later.