The GT300/Fermi Thread - Part 2!

[***Deimos***]

So NVIDIA should just say "sorry dudes and dudettes, but Fermi won't beat HD 5970 so we ain't gonna relase it"? What would be the point of that?

Fermi might not be the new messiah for gamers, but as quite few already pointed out Fermi has unique HPC-capabilities.

A product that might not sell well to gamers but do "quite" good in HPC-applications is better than no product at all, don't you think?

Sometimes you've got to release what you got, no matter what. Don't you think ATI didn't like what R600 turned out to be? RV670 was basically R600 done right but wasn't really faster. Should they not have released RV670 because it was late and not fast enough?

Wake up NapalmV5! WTH happened to you?!

You are right about the parallels to R600.. big, power hungry, late and overhyped.

In the end though, regardless what the outcome of Fermi is, the market will move on to new products.

Already 2 years ago nVidia engineers created architecture for DX11 successor, and right now they are designing it with lessons learned from Fermi.

But, nVidia's make chips bigger and bigger mentality is becoming their acheles heel. As the inside look into AMD showed, changing course (convincing EVERYONE to do things differently) is difficult. 90-95% chance that GT400/"Fermi2" will be big monolithic design... probably 28-32nm shrink of Fermi.

After that, in 2012, (if Fermi doesnt do it) nVidia might be first to break 645.16 mm^2 barrier. ie a chip so big its 1 square inch, on a wafer thats only 37.7 inch^2.

JUST IN CASE BACK IN SEPT 30, 2009 YOU WEREN'T SHOCKED THAT FERMI IS 3BT.. some perspective:
45nm Phenom II 6MB L3 = 258mm2
45nm Core i7 8MB L3 = 263mm2 - tiny in comparison
45nm 6core Dunnington 16MB L3 (Core2) = 503mm2
45nm 8core SMT POWER7 32MB eDRAM = 567mm2
65nm 240SP GT200 = 576mm2 - redefining ridiculously huge
45nm 8core SMT Tukwila Itanium 24MB L3 ~700mm^2 and 2BT.
40nm 512SP Fermi = ?? record die size ?? - 3BT is record!!??

BTW: if anandtech Inside RV870 article is true about TSMC 40nm, bad news for Fermi. Via defects, and doubling to compensate, and having more redundant logic/ALU will bloat an already enormous die size. Likewise transistor channel length varience bigger problem for Fermi since chip already hot enough.