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Thread: AMD talks up its first Fusion chip

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    AMD talks up its first Fusion chip

    CHIP DESIGNER AMD has been talking up some of the x86 design features for its first Fusion processor at the International Solid State Circuits Conference (ISSCC) in San Francisco this week.

    The upcoming 'Llano' Accelerated Processing Unit (APU) will see the joining of a 32nm silicon-on-insulator (SoI) Phenom II quad core CPU with a DirectX 11 capable GPU on the same die. This is a more sophisticated approach than Intel's at present, in which it simply adds a GPU chip to the processor package and calls that 'integrated'.

    http://www.theinquirer.net/inquirer/...ks-fusion-chip

    http://www.eetimes.com/news/latest/s...2700324&pgno=2


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    Oh dear, and again we see the monolithic bs card in game....

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    Quote Originally Posted by Hornet331 View Post
    Oh dear, and again we see the monolithic bs card in game....
    Who cares about monolithic versus 2 separate dies? It's performance per watt that matters. I don't care how any company gets there.
    As quoted by LowRun......"So, we are one week past AMD's worst case scenario for BD's availability but they don't feel like communicating about the delay, I suppose AMD must be removed from the reliable sources list for AMD's products launch dates"

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    It seems that whenever Intel has no competition, it becomes complacent. AMD seems to be far more innovative than Intel lately, even if its performance isn't as high end.

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    The Llano's RV8xx DX11 part with 400+ stream processors will simply be in its own league when it comes to performance... Add in the hybrid CF capability with discrete cards and I can't see what kind of redesign the current Intel GMA series need to receive to be even closely competitive with Llano's GPU when Intel integrates them into SB cores.

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    Quote Originally Posted by informal View Post
    The Llano's RV8xx DX11 part with 400+ stream processors will simply be in its own league when it comes to performance... Add in the hybrid CF capability with discrete cards and I can't see what kind of redesign the current Intel GMA series need to receive to be even closely competitive with Llano's GPU when Intel integrates them into SB cores.
    This will rock if the driver support is decent...
    And hope OCing will be just as good as for Intel chips, too!
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    Quote Originally Posted by Hornet331 View Post
    Oh dear, and again we see the monolithic bs card in game....
    ? (i love these emoticons)

    if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.
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    Quote Originally Posted by freeloader View Post
    Who cares about monolithic versus 2 separate dies? It's performance per watt that matters. I don't care how any company gets there.
    exactly this, it doesn't matter if its one die or not.

    Quote Originally Posted by god_43 View Post
    ? (i love these emoticons)

    if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.
    see above.

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    Core = 9.69mm^2
    Core + L2 ~ 1.5x of that? = ~15mm^2

    So basically quadcore logic under 90mm^2 (+IMC,HTPad...)?


    IMO the total die size should be 140-180mm^2 or so, but no longer do they have to sell it at $99- fetching double the price should be easy, not that it would be a good purchase for desktop.

    For laptops though I think this should be their way in, especially with the emphasis on power management- seems to me that this is a laptop oriented design for the most part, being able to target $300+ ASPs that AMD could previously only dream about.
    Last edited by Macadamia; 02-08-2010 at 02:59 PM.
    Quote Originally Posted by radaja View Post
    so are they launching BD soon or a comic book?

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    i don't think this is for laptops, this will not include BD cores. The number of transistors show us that.

    maybe i'm wrong, but laptops will come with BD cores. My point of view this is for smaller than laptops, maybe single core for iPad of Micro$oft. With a GPU this could be an Ipad killer.

    good night ^^

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    Quote Originally Posted by Kai Robinson View Post
    It seems that whenever Intel has no competition, it becomes complacent. AMD seems to be far more innovative than Intel lately, even if its performance isn't as high end.
    That's normal for an underdog imho. If you can't beat your big competitor in the field ppl care the most try to be innovative.

    Big companies (especially when they nearly have a monopoly) tend to become slow and uninnovative (does this word even exist?).
    Notice any grammar or spelling mistakes? Feel free to correct me! Thanks

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    Quote Originally Posted by god_43 View Post
    ? (i love these emoticons)

    if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.
    It's not bad, it's just irrelevant unless it brings a performance increase or power cut.
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    Quote Originally Posted by Macadamia View Post
    Core = 9.69mm^2
    Core + L2 ~ 1.5x of that? = ~15mm^2

    So basically quadcore logic under 90mm^2 (+IMC,HTPad...)?


    IMO the total die size should be 140-180mm^2 or so, but no longer do they have to sell it at $99- fetching double the price should be easy, not that it would be a good purchase for desktop.

    For laptops though I think this should be their way in, especially with the emphasis on power management- seems to me that this is a laptop oriented design for the most part, being able to target $300+ ASPs that AMD could previously only dream about.
    Later die pictures showed more GPU area so the die for so far is ~205mm^2



    Regards, Hans

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    Quote Originally Posted by Hans de Vries View Post
    Later die pictures showed more GPU area so the die for so far is ~205mm^2



    Regards, Hans
    why there are 4 hypertransport links?

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    Quote Originally Posted by qcmadness View Post
    why there are 4 hypertransport links?
    Just a guess...Hans will obviously know more.

    1 HT link to the GPU.
    1 or 2 HT link(s) between the CPU cores.
    1 HT link to the rest of the system. (PCI-E bus, southbridge, add in card, etc...)
    Last edited by freeloader; 02-08-2010 at 07:25 PM.
    As quoted by LowRun......"So, we are one week past AMD's worst case scenario for BD's availability but they don't feel like communicating about the delay, I suppose AMD must be removed from the reliable sources list for AMD's products launch dates"

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    Quote Originally Posted by freeloader View Post
    Just a guess...Hans will obviously know more.

    1 HT link to the GPU.
    1 or 2 HT link(s) between the CPU cores.
    1 HT link to the rest of the system. (PCI-E bus, southbridge, add in card, etc...)

    Yes, interesting all these HT links... They are half width but probably
    almost as fast as the full width HT's used up to now (>=6.4GHz)

    Maybe for 2 dies per package for higher performance desktops?

    or also for the HPC market (CRAY) to build supercomputers getting
    a whole lot more TFlops from the GPU's?

    or maybe one is used to transport monitor output data to the
    South bridge?

    Regards, Hans
    Last edited by Hans de Vries; 02-08-2010 at 08:10 PM.

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    So any idea how these will perform?

    Close to a Phenom II and ... ?


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    Quote Originally Posted by Otis11 View Post
    So any idea how these will perform?
    Close to a Phenom II and ... ?
    Porpus-based and double L2 cache, should be similar with PII performance.

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    Quote Originally Posted by Hans de Vries View Post
    Yes, interesting all these HT links... They are half width but probably
    almost as fast as the full width HT's used up to now (>=6.4GHz)

    Maybe for 2 dies per package for higher performance desktops?

    or also for the HPC market (CRAY) to build supercomputers getting
    a whole lot more TFlops from the GPU's?

    or maybe one is used to transport monitor output data to the
    South bridge?

    Regards, Hans
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    When intel was using MCM, they said it was a better solution than native dies. Until they got native dies. (To be fair, we knocked *unconnected* MCM, and still do, we never knocked MCM as a technology, so hold your flames.)
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    cheers

    Quote Originally Posted by Hans de Vries View Post
    Yes, interesting all these HT links... They are half width but probably
    almost as fast as the full width HT's used up to now (>=6.4GHz)

    Maybe for 2 dies per package for higher performance desktops?

    or also for the HPC market (CRAY) to build supercomputers getting
    a whole lot more TFlops from the GPU's?

    or maybe one is used to transport monitor output data to the
    South bridge?

    Regards, Hans
    hmmmm the latter makes a lot of sense... but do they need a seperate HT link for that? thats what confused me about intel as well, why dont they use that massive qpi bus to move all the display data

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    Have we seen stacked HT links before???
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    Quote Originally Posted by qcmadness View Post
    Porpus-based and double L2 cache, should be similar with PII performance.
    how do you know its porpus based? besides many different improvements, it was my understanding that it would be based on the latest phenom core? i am sure there are plenty of details left out.
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    is dual channel ddr3 going to be enough bandwidth for both the gpu and cpu?

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