P55-UD3R incorrect CAS latency setting

[FELIX]

I think "Static tRD" is the same timing that "Read and merging-write window" in cpu-tweaker. (in this case, I'll rename it in the finale version)
It's possible that when you change the "Read and merging write" timing with cpu-tweaker, Cas# change in cpu-z,
cause these timings are exactly at the same register address in P45 chipset.
I use an other address in cpu-tweaker, but I'm not sure that it's right...