AMD cuts to the core with 'Bulldozer' Opterons

[Dresdenboy]

"Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore.

"My understanding is that the subsequent thermal steps are causing problems with the gate-first approach," said a senior vice president at Qualcomm Corp. (San Diego) who was attending IEDM. "GlobalFoundries seeks a gate-last approach, and if necessary they could drop in a gate-last module independent of IBM," the Qualcomm executive said.

http://www.semiconductor.net/article...igh_k-full.php

Translation : yeah, it might work at 32nm, but obviously yields are down the drain. Exactly what foundries want to hear.
It is one thing to show a few transistors or a small SRAM from R&D, it's a completely different thing to get a production process ready to roll. IBM utterly sucks at the later.

Same site, same topic, different result:
http://www.semiconductor.net/article...Generation.php

Seems, we have to wait and watch how the story unfolds.

[Chumbucket843]

@dresdenboy. this is from your blog.

Does someone have an idea, what EBO is?

perhaps endian byte order?

[Dresdenboy]

@dresdenboy. this is from your blog.

perhaps endian byte order?

Ah, OK. This riddle is already solved. Please have a look at the comments to my blog entry.

[freeloader]

Hey, someone has to assume the role of the optimist!

Hopefully AMD is not going down the same road as Intel tried to with the P4 Netburst path or if they are, hopefully they've
learned enough to not make the mistakes Intel did. I had a Prescott that I could literally heat up my computer room with.

[qcmadness]

Hey lemme the same 1 "doom"y sentence from the same article written by the same source!

I can be an anal-yst now ey? XD


Oh BTW Intel can't even get the mobile Arrandales to perform properly (stuck at 1.8Ghz) on battery load, so much for static logic, high-k, and such a superior gate-first approach with smart core gating.

IMC design is not good for battery performance

while you shut down cpu, you cannot power down imc because (i)gpu needs it

[god_43]

something about this design makes me believe that ipc is going to be really high? intel has 4 per cycle right? or do i have this mixed up with something else?

[qcmadness]

something about this design makes me believe that ipc is going to be really high? intel has 4 per cycle right? or do i have this mixed up with something else?

the max. ipc per module (dual-core):
INT: 4
64-bit FP: 4
128-bit FP: 2
256-bit FP: 1

Total issue: 4



if the ALU and FPU are clocked as the same

[god_43]

the max. ipc per module (dual-core):
INT: 4
64-bit FP: 4
128-bit FP: 2
256-bit FP: 1

if the ALU and FPU are clocked as the same

oh.......that is certainly interesting? is this on par with what intel has now then?

[qcmadness]

oh.......that is certainly interesting? is this on par with what intel has now then?

Not much info for Sandy Bridge except 256-bit AVX extensions (SSEx is 128-bit)

Nehalem / Westmere:


IPC:
INT: 3 (+2)
FP / SSE: 3

Total issue: 4

[informal]

According to AMD's Rick Bergam,each core inside the module is 4 issue wide,so at the module level INT capability is 2x of that,while FP is also 4 issue with 256bit AVX and FMAC capability(FMAC practically stomps anything we have today in x86 world as far as fp/sse stuff goes).

[qcmadness]

According to AMD's Rick Bergam,each core inside the module is 4 issue wide,so at the module level INT capability is 2x of that,while FP is also 4 issue with 256bit AVX and FMAC capability(FMAC practically stomps anything we have today in x86 world as far as fp/sse stuff goes).

http://www.anandtech.com/cpuchipsets...oc.aspx?i=3674

Within each integer “core” are four pipelines, presumably half for ALUs and half for memory ops. That’s a narrower width than a single Phenom II core, but there are two integer clusters on a single Bulldozer core.

Currently each K10 integer pipeline can do both ALU and memory ops.

[informal]

Note the key word in AT's speculative article:

Within each integer “core” are four pipelines, presumably half for ALUs and half for memory ops.

In other words he presumes. You have a diagram from AMD stating 4 pipelines(non segmented into ALUs and AGUs). I'm not saying it's 4 issue being made of grouped 4 ALUs/AGUs ,it may be 2 issue with throughput of 4 issue(look at dresdenboy's blog),but I'm still sticking to the image and the post analyst call interview with Rick Bergam who stated that each core inside the module is a 4 issue core.

PS Note that in the diagram of 10h you posted,the ALUs and AGUs are grouped together,in pairs... 3 issue made up of 3 groups of ALUs and AGUs. Very same methodology may apply to BD cores .

[qcmadness]

Note the key word in AT's speculative article:

In other words he presumes. You have a diagram from AMD stating 4 pipelines(non segmented into ALUs and AGUs). I'm not saying it's 4 issue being made of grouped 4 ALUs/AGUs ,it may be 2 issue with throughput of 4 issue(look at dresdenboy's blog),but I'm still sticking to the image and the post analyst call interview with Rick Bergam who stated that each core inside the module is a 4 issue core.

PS Note that in the diagram of 10h you posted,the ALUs and AGUs are grouped together,in pairs... 3 issue made up of 3 groups of ALUs and AGUs. Very same methodology may apply to BD cores .

speculations here

if each core in the module has 4 independent ALU and AGUs, the core will be "swelled" and may get too big.

my image for 2 ALU arguments comes from
1. post above (average integer IPC is about 2)
2. bobcat diagram (very similar to half of a bulldozer module)


if the architecture is for server space, then it sounds possible to have only 2 ALU per core as each thread for server application is of low IPC but highly-threaded (>24 thread).

[informal]

speculations here

if each core in the module has 4 independent ALU and AGUs, the core will be "swelled" and may get too big.

my image for 2 ALU arguments comes from
1. post above (average integer IPC is about 2)
2. bobcat diagram (very similar to half of a bulldozer module)


if the architecture is for server space, then it sounds possible to have only 2 ALU per core as each thread for server application is of low IPC but highly-threaded (>24 thread).

BD and bobcat were developed by 2 different teams with 2 different goals in mind... While they do share some common ideas,Bobcat is targeted at very low power and good mainstream performance ,while BD is targeted for very high performance with advanced power gating technologies in place to control the power draw in various scenarios. Note also that Bobcat has no support for various ISA extensions BD will support and has a much weaker fp unit with no FMAC capability(which is normal for low power design).

As for the "swelled" comment,you seem to forget that BD is going to be produced @ 32nm node,so no,the cores won't be that big in any case. The module itself is probably even going to be smaller than one SB core(with SMT),courtesy of the way AMD designed the very BD module ...

[qcmadness]

BD and bobcat were developed by 2 different teams with 2 different goals in mind... While they do share some common ideas,Bobcat is targeted at very low power and good mainstream performance ,while BD is targeted for very high performance with advanced power gating technologies in place to control the power draw in various scenarios. Note also that Bobcat has no support for various ISA extensions BD will support and has a much weaker fp unit with no FMAC capability(which is normal for low power design).

As for the "swelled" comment,you seem to forget that BD is going to be produced @ 32nm node,so no,the cores won't be that big in any case. The module itself is probably even going to be smaller than one SB core(with SMT),courtesy of the way AMD designed the very BD module ...

even with 32nm, the BD core is not small though.

Shanghai / Deneb single core: ~19mm^2 / 55M transistor
Calculated BD module: ~29mm^2 / 165M transistor (assuming 50% die shrink, ~150% die size claimed from AT's communication with AMD)

Packing 4 modules with 8MB L3 cache, you still get about 180mm^2 die size.

[madcho]

i think the two arrow on the diagram are very clear.

AMD is doing big brute force ultra wide pipelines for BD cores.

[haylui]

even with 32nm, the BD core is not small though.

Shanghai / Deneb single core: ~19mm^2 / 55M transistor
Calculated BD module: ~29mm^2 / 165M transistor (assuming 50% die shrink, ~150% die size claimed from AT's communication with AMD)

Packing 4 modules with 8MB L3 cache, you still get about 180mm^2 die size.

don't rely to a SINGLE source only

[Florinmocanu]

even with 32nm, the BD core is not small though.

Shanghai / Deneb single core: ~19mm^2 / 55M transistor
Calculated BD module: ~29mm^2 / 165M transistor (assuming 50% die shrink, ~150% die size claimed from AT's communication with AMD)

Packing 4 modules with 8MB L3 cache, you still get about 180mm^2 die size.

1 BD module = 2 Deneb cores.


So, 165 M vs 110 M for 2 deneb cores, 29mm vs 38mm. Performance should be higher as well, so i think they are doing a good job.

[savantu]

That's a pretty bold statement given the current indications that Bulldozers are heading for an early rather than late release versus their official late 2010 release date.

How exactly is it early when AMD slides themselves point out it is a 2011 product. Not only that but assuming perfect execution by AMD ( which I really doubt ), everything is at the mercy of GF. Which btw, has some issues with process technology.

[Florinmocanu]

Savantu, does intel pay your bills? Does it make breakfast for you? Because from how you post, it looks that way.

Somehow, you want AMD to fail, you want them to be late with this product. Nothing from what we know about bulldozer can make us think they will be late, they seem to move fast into the right direction.

[informal]

How exactly is it early when AMD slides themselves point out it is a 2011 product. Not only that but assuming perfect execution by AMD ( which I really doubt ), everything is at the mercy of GF. Which btw, has some issues with process technology.

AMD is targeting BD class cores for desktop and server for Q2 next year.Think Thuban time frame + 1 year away(Thuban is May this year).

[haylui]

How exactly is it early when AMD slides themselves point out it is a 2011 product. Not only that but assuming perfect execution by AMD ( which I really doubt ), everything is at the mercy of GF. Which btw, has some issues with process technology.

the AMD today is not the AMD you knew yesterday
lolz

[informal]

BD cores get sported by HWinfo app.
Gen. 15h,code name Bulldozer. Since BD samples are in AMD's hands,it's logical they get support from some HW identification app. out there.

http://www.hwinfo.com/

Intel Nehalem family: Core i7 (Bloomfield), Xeon 55xx (Nehalem-EP/Gainestown), Xeon W35xx (Nehalem-WS), Nehalem-EX (Beckton), Core i5/i7 (Lynnfield), Core i7 (Clarksfield), Havendale, Auburndale, Xeon (Jasper Forest)
Intel Westmere family: Core i3/i5 Clarkdale, Core i5/i7 Arrandale (+ECC), Westmere-EP, Westmere-WS, Gulftown, Westmere-EX (Eagleton)
Intel EP80579 (Tolapai), Atom Z5xx (Silverthorne), Atom N2xx/2xx/3xx (Diamondville), Atom N4xx/D4xx/D5xx (Pineview), Atom (Lincroft)
Intel Sandy Bridge family
AMD Family 10h (DR-Ax/Bx, RB-Cx, BL-Cx, DA-Cx, HY-Dx, PH-Ex):
- AM2r2/AM3: Athlon/Sempron (Lima, Sargas), Athlon II/Neo (Kuma, Regor, Rana, Propus), Phenom II/Neo (Agena, Deneb, Callisto, Heka, Toliman), TWKR Black Edition
- Fr2/Fr4: Opteron (Barcelona, Shanghai, Suzuka, Budapest, Istanbul)
- G34: Opteron 61xx (Magny Cours)
- S1g3/g4: Turion II/Ultra, Athlon II, Phenom II
- ASB2: Athlon II Neo K, Turion II Neo K
AMD Family 11h (LG-Ax/Bx): S1g2: Sempron SI/NI/X2, Athlon QI/QL (Sable), Turion X2 Ultra/RM (Griffin)
AMD Family 12h (FS1)
AMD Family 15h: Bulldozer
VIA C7 and Nano

[god_43]

intel must know about bulldozers supposed capabilities already eh? i mean intel must have like spy's inside amd (corporate espionage is a big deal you know) im sure? should amd have released any info about these new cpus? is sandyB a new arch, or is it a refresh of nehielem? wont intel be able to counter amd with this info? and why is it snowing out side?

sometimes i think about these things...

[ajaidev]

Amm Intel did delay Sandy bridge and they did it to try and implement something which SB does not have and BD does. Tough the implementation is very hard to accomplish i have been told 3-4 teams are working on it right now, one may call it the v1.1 the v1.0 of SB is all ready for the fight....

If the v1.1 works out it will get relesed in stead of the v1.0 otherwise v1.0 will be used, in tis case IB will come sooner than later.