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[Calmatory]

Where are we getting that each shader can do 3ops per clock?
From what I have read, the MUL is gone, and it can do 2ops per clock.
Depending on clocks it will be under 2TFlops for SP and under 1TFlops for DP, somewhere around 600-900GFlops DP.

Can anyone point out where they are getting 3ops per clock for GF100?

http://forums.nvidia.com/lofiversion...hp?t73056.html

At least that says TPU can do some operations per cycle, which adds one FLOP to the MAD, which counts as two FLOPs alone. Marketting talk.

[LordEC911]

http://forums.nvidia.com/lofiversion...hp?t73056.html

At least that says TPU can do some operations per cycle, which adds one FLOP to the MAD, which counts as two FLOPs alone. Marketting talk.

Yes, that is for G200, it has a date of 2008 on there.
People are thinking that GF100 has the same setup as G200?

Edit- Found the whitepaper where I read it. http://www.nvidia.com/content/PDF/fe...Whitepaper.pdf

SP-512FMA ops per clock
DP-256FMA ops per clock