I read that, but thats what i m asking, if it communicates to the cpu at pci-e 16... doesnt that necessarily limit the amount of instructions it can send to the gpus at 16lanes.. ie 1x16, 2x8, or 4x4?Originally Posted by m0da
I think this quote from the article will help:
The way I read it is that the chip communicates with CPU with a single x16 lane; It subsequently communicates with the GPUs with a 4x8, 2x16, or 1x16 interface.
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