Lynnfield P55 - B2B Performance

[Raja@ASUS]

B2B sets a delay for the number of memory clock cycles to pass before a read is processed.

Values below 4 don't work on i7 (apart from 0 to disable the logic), so 1-3 will default to 4.

RTL is the number of Uncore clocks that pass before data arrives at a pad in the IMC.

Main performance is locked away in the post equation (some of these parameters are available to adjust).