Originally Posted by
gznp
I still don't get what this slide suggests - if the PCIe has a bandwidth of 2.5 Gb/s and LIMITS the SATA controller, why doesn't this happen to all our current motherboards? Or does it happen but we don't notice it? Does the Revolution or the SuperComputer have a similar PLX-design for their SAS controller?
It seems weird to me, linking the Marvell chip or any other SATA controller on the PCIe lanes and their bandwidth...
And you know what? If this is the case indeed and the SATA-3 controller gets limited by the PCIe lane, then this thing that ASUS did is purely immature, and saaya is right to "troll" at them.
You know why? Because I know that the Marvell chip wasn't supposed to be out at the time being, but they implemented it purely for marketing reasons. If the SATA-3 needs a PCI-Express 3.0 lane in order to work at full bandwidth, then they should have waited and not make a quick fix via the PLX chip (and call it a revolution!!). Heck, we don't even have the SATA-3 HDDs/SSDs, it is a simple move of "domination" over the other brands.
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