X48 Rampage Formula Preview.

[leo27]

i've been reading this forum ever since i got my rampage formula, finally i can post after a few registration issues.

my rig is:
Antec P182
asus rampage formula x48 Bios 803
q6600 G0 @ 3.4Ghz
Gskill F2-6400CL4-2GBPI-B @850Mhz
TRUE with 2 noctua P12 Push/Pull

my settings (25 Linx 64-bit stable, Prime95 small and large fft's stable)

*Extreme Tweaker*
Ai Overclock Tuner [Manual]
OC From CPU Level Up [Auto]
CPU Ratio Setting [08.0]
FSB Strap to North Bridge [400]
FSB Frequency [425]
PCIE Frequency [100]

DRAM Frequency [DDR2-850MHz]
DRAM Command Rate [2N]
DRAM CMD Skew on Channal A [Greyed Out]
DRAM CMD Skew on Channal B [Greyed Out]
DRAM CLK Skew on Channal A [Auto]
DRAM CLK Skew on Channal B [Auto]

DRAM Timing Control [Manual]
1st Information
CAS# Latency [4]
RAS# to CAS# Delay [4]
RAS# PRE Time [3]
RAS# ACT Time [9]
RAS# to RAS# Delay [3]
REF Cycle Time [40]
WRITE Recovery Time [6]
READ to PRE Time [3]
2nd Information
READ to WRITE Delay (S/D) [7]
WRITE to READ Delay (S) [3]
WRITE to READ Delay (D) [4]
READ to READ Delay (S) [4]
READ to READ Delay (D) [5]
WRITE to WRITE Delay (S) [4]
WRITE to WRITE Delay (D) [5]
3rd Information
WRITE to PRE Delay [12]
READ to PRE Delay [3]
PRE to PRE Delay [1]
ALL PRE to ACT Delay [4]
ALL PRE to REF Delay [4]

DRAM Static Read Control [Enabled]
Ai Clock Twister [Stronger]
Ai Transaction Booster [08]
Pull-in of CHA PH1 [Enabled]
Pull-in of CHA PH2 [Enabled]
Pull-in of CHA PH3 [Enabled]
Pull-in of CHA PH4 [Enabled]
Pull-in of CHB PH1 [Enabled]
Pull-in of CHB PH2 [Enabled]
Pull-in of CHB PH3 [Enabled]
Pull-in of CHB PH4 [Enabled]

CPU Voltage [1.41250v] (1.4V in windows)
CPU PLL Voltage [1.50v]
North Bridge Voltage [1.37v]
DRAM Voltage [1.84v]
FSB Termination Voltage [1.32v]
South Bridge Voltage [1.05v]
SB 1,5V Voltage [1.50v]
Loadline Calibration [Enabled]
CPU GTL Voltage Reference [0.65x]
NB GTL Voltage Reference [0.67x]
DRAM Controller Voltage REF [AUTO]
DRAM Channel A Voltage REF [AUTO]
DRAM Channel B Voltage REF [AUTO]

CPU LED Selection [CPU Voltage]
NB LED Selection [North Bridge Voltage]
SB LED Selection [South Bridge Voltage]
Voltiminder LED [Enabled]

CPU Spread Spectrum [Disabled]
PCIE Spred Spectrum [Disabled]
Cpu Clock Skew [Delay 200ps]
NB Clock Skew [Delay 100ps]

Now i have run into a problem in that i was unable to reduce the memory timings (4-4-4-12 at 1.92V in bios) with a PL7, however if i run PL8 with all phase pull-ins as above then i can achieve the timings and voltage shown in the settings above (4-4-3-9 at 1.84V).

I take it PL8 with all Pull-ins is equivalent to PL7?????

to A-GREY
I've read that you use UT2004 to determine the FSB termination voltage. What settings do you use in UT2004????
and do you run it with Prime95 small fft's or large fft's????
an explanation of the procedure would be appreciated.

Lastly is a CPU GTL of 0.65x recommended for a 65nm processor or is 0.63x advised.

Thanks for your help and keeping up with this thread. It is a invaluable resource for overclocking this board.