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With 2 seperate PLL's, period jitter and random jitter of both reference clock signals will be out of phase at the synthesizer of downstream busses (the jitter has nothing to do with clock skew per se btw). Depends how the associated sampling windows are affected by that (when the opposite clock domain has a seperate master oscillator). You might get a smaller logic sampling window as a result, at which point some form of skew might help, but you'll still be playing with narrower sampling margins if the jitter is excessive. I should add though that the associated synthesizer of each clock signal will add its own jitter to the reference clock (regardless of the reference clock source). We have no external high speed interconnect like QPI on i5, i7 and beyond is where master clock jitter is really becoming a big deal. The proof will be in the final oc limits I guess.
Last edited by Raja@ASUS; 07-24-2009 at 08:51 PM.
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