X48 Rampage Formula Preview.

[greg.m]

With 9 X 465MHz and DDR 1117MHz tRD 7. When Chemjsal can get that stable with 8 Giga you should have no problem to have it IntelBurnTest stable with the G.SKILL F2-9600CL5D-4GBPI.

When you can't get that stable and I can get it stable with 8 X 465MHz it must be a compatibility between the memory and the board.

Try with advancing the DRAM CLK Skew on Channel A and B with 100ps to if you can keep your memory more stable.

Here is some screenies:




and 0803 settings:

Ai Overclock Tuner [Manual]
CPU Ratio Setting [8.0]
FSB Strap to North Bridge [Auto]
FSB Frequency [465MHz]
PCIE Frequency [105MHz]

DRAM Frequency [1117MHz]
DRAM Command Rate [Auto]
DRAM CLK Skew on Channel A/B [Auto]
DRAM TimingControl [Manual]-5-5-5-15
DRAM Static Read Control [Enabled]
Ai Clock Twister [Moderate]
Ai Transaction Booster [Manual]
Common Performance Level [07]
Pull-In of CH A/B all disabled

CPU Voltage [1.29375]-> i changed that @ 1.275 and run linx
CPU PLL Voltage [1.50V]
North Bridge Voltage [1.45V] - 1.44V real
DRAM Voltage [2.10V]
FSB Termination Voltage [1.34V] - 1.25V real
South Bridge Voltage [Auto]
SB 1.5V Voltage [Auto]
Loadline Calibration [Enabled]
CPU GTL Voltage Reference [0.63X]
NB GTL Voltage Reference [0.67X]
DRAM Controller Voltage REF [Auto]
DRAM Channel A/B Voltage REF [Auto]

CPU Spread Spectrum [Disabled]
PCIE Spread Spectrum [Disabled]
CPU Clock Skew [Normal]
NB Clock Skew [Normal]


CPU Ratio Setting [8.0]
C1E Support [Disabled]
CPU TM Function [Disabled]
Vanderpool Technology [Disabled]
Execute Disable Bit [Enabled]
Max CPUID Value Limit [Disabled]
Intel(R) SpeedStep (TM) Tech. [Disabled]

as you can see i used a bit high voltages because i wanted to be sure that they wouldnt cause any prob.

[Alien Grey]

Here is some screenies:




and 0803 settings:

Ai Overclock Tuner [Manual]
CPU Ratio Setting [8.0]
FSB Strap to North Bridge [Auto]
FSB Frequency [465MHz]
PCIE Frequency [105MHz]

DRAM Frequency [1117MHz]
DRAM Command Rate [Auto]
DRAM CLK Skew on Channel A/B [Auto]
DRAM TimingControl [Manual]-5-5-5-15
DRAM Static Read Control [Enabled]
Ai Clock Twister [Moderate]
Ai Transaction Booster [Manual]
Common Performance Level [07]
Pull-In of CH A/B all disabled

CPU Voltage [1.29375]-> i changed that @ 1.275 and run linx
CPU PLL Voltage [1.50V]
North Bridge Voltage [1.45V] - 1.44V real
DRAM Voltage [2.10V]
FSB Termination Voltage [1.34V] - 1.25V real
South Bridge Voltage [Auto]
SB 1.5V Voltage [Auto]
Loadline Calibration [Enabled]
CPU GTL Voltage Reference [0.63X]
NB GTL Voltage Reference [0.67X]
DRAM Controller Voltage REF [Auto]
DRAM Channel A/B Voltage REF [Auto]

CPU Spread Spectrum [Disabled]
PCIE Spread Spectrum [Disabled]
CPU Clock Skew [Normal]
NB Clock Skew [Normal]


CPU Ratio Setting [8.0]
C1E Support [Disabled]
CPU TM Function [Disabled]
Vanderpool Technology [Disabled]
Execute Disable Bit [Enabled]
Max CPUID Value Limit [Disabled]
Intel(R) SpeedStep (TM) Tech. [Disabled]

as you can see i used a bit high voltages because i wanted to be sure that they wouldnt cause any prob.

Thanks greg.m for testings this. I'll try changing the PCIe frequenty like you did and see if I can get it stable with these settings. When this is stable I should get it stable with DDR 1239MHz and trd 6 too.