Thank you much again, Tony. It's exactly what I wanted to see. I think I'm starting to get to know about PII. And probably you've known about it all along. :P My hypothesis regarding PII architecture from your tables above:
1. When data can be replenished from L3, K10's performance keeps increasing to NB frequency, until it reaches the same frequency as the core frequency.
2. When data needs to be fetched from system memory, increasing NB frequency alone will give diminishing returns unless memory can keep up with it. Ideally it should be [NB frequency = 2 x memory frequency] (dual-channel)
So in my imagination, a 'perfect' 955BE would be 3.2GHz core / 3.2 GHz NB / dual-channel DDR2-1600 or higher.
Does this make sense to you, or am I totally wrong?
Bookmarks