AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

Agner Fog's comment on this from Ace's hw:

Thanks for posting the reference to the new AMD manual, indicating that AMD have changed their SSE5 codes for the sake of compatibility with Intel AVX and FMA.

The present situation shows once again that such a committee is desperately needed. Unfortunately this is not gonna happen unless somebody can legally force Intel and AMD to cooperate rather than keeping secrets to each other.

If Intel and AMD had communicated better we wouldn't have this mess now.

The new instruction space that has been opened with Intel's introduction of the VEX coding scheme is HUGE. It has room for all kinds of extensions and new instuctions for many years to come without making instruction codes longer. It would be absolutely no problem to reserve a small part of this new instruction space to AMD so that they could invent new instructions without risking that Intel has something else in their pipeline that happens to use the same code for something else. However, the new spec. of AMD instructions indicates that it has been impossible for AMD to get such an agreement with Intel. Rather than coding their new instructions according to the VEX scheme, they have invented yet another prefix called XOP. The AMD XOP prefix (8F) works in exactly the same way as Intel's VEX prefix (C4). This makes instruction decoding easier than if AMD had sticked to their SSE5 coding scheme. If some of the new instructions invented by AMD happen to be so popular that Intel have to copy them, then Intel can just treat 8F and C4 as equivalent, and the new instruction fits into the VEX scheme. The codes do not overlap, even if 8F and C4 are treated as equivalent. (8F would overlap with POP instructions if used instead of C4 on some Intel instructions).

The blame here is really on Intel. They have changed their specifications for FMA instructions without informing AMD in time. They must have known that AMD had plans about changing their coding scheme to make it compatible with Intel's because there have been patent-clearing negotiations between the two companies about this issue.

Intel should also be blamed for refusing to assign part of the opcode space to AMD, thereby forcing them to invent yet another prefix.

It seems that AMD are the nice guys in this case. They have made great sacrifices by dropping their SSE5/DREX coding scheme and replacing it with Intel's scheme for the sake of compatibility. And then Intel have blown it all by changing their specs once again. Arghhhhh!!!!!!

How long shall we live with this race between Intel and AMD on inventing new instructions and the resulting problems of incompatibility, a bloating and complicated opcode map, and instructions that are rarely used becaused the competitor has invented something better? These obsolete instructions will have to be supported in all future for the sake of compatibility with legacy software.